JPS59226955A - Program debug device - Google Patents

Abstract

PURPOSE:To detect easily a broken area of a memory which is due to a fault produced during the program debug by providing plural address comparator and recording the input/output data between the check start and end addresses which are set previously. CONSTITUTION:A range of addresses to be checked is first set when a test is carried out. In other words, a check start address is set by a switch STA, and a check end address is set by a switch SPA respectively. Then the data between the set check start and end addresses is recorded in response to the traveling of the program via the 1st, 2nd and 3rd comparators ST.MAT, BL.MAT and SP.MAT respectively. In other words, the input/output data are all recorded in an RAM. With use of these data, a broken area of a memory which is due to a fault generated during the program debug can be detected compared with the conventional case.

Description

Detailed Description of the Invention (a) 0 Technical Field of the Invention The present invention relates to a program depacking device, and more particularly to a program depacking device having a function of searching for memory destroyed while depacking a created program. be.

(Mountain), Prior Art and Problems When creating a program to drive a data processing device and actually running that program, various program errors may occur, such as destroying memory. need to be depacked.

Depacking such a program is a very complicated job and requires skill.

(C)6 OBJECTS OF THE INVENTION It is an object of the present invention to provide a program deblocking device for locating memory corruption locations that occur during program depacking in order to improve the conventional program creation situation.

(d)0 Structure of the Invention According to the present invention, in a system having a processor and a memory, at least address information and write data information of the signals for accessing the memory are received from the processor. and comprises a first address comparison circuit, a second address comparison circuit, and a third address comparison circuit, and inputs all or part of the address information to an input terminal of one of the three address comparison circuits. Then, the check start address of the program to be checked is input to the other input terminal of the first address comparison circuit, and the check start address of the program to be checked is input to the other input terminal of the second address comparison circuit. input the address of the memory to be checked, input the end address of the program to be checked into the other input terminal of the third address comparison circuit, and after the time when the first address comparison circuit matches, The second address comparison circuit writes the write data information of the address information, which has found a match, to the random access memory in the device according to the address information, and the third address comparison circuit finds a match. This is achieved by providing a program depacking device characterized in that the write operation is stopped when the write operation is performed.

(e) 0 Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of the invention. In the figure, CPU is a processor, MEM is a memory, 10C is an input/output device, 5BUS is a system bus, and PDBG is a program depacking device according to the present invention.

FIG. 2 is a diagram illustrating one embodiment of a system bus according to the present invention. In the figure, REQ is a bus access signal, ACK is a response signal to the bus access signal REQ, and MEM/
IO is access to memory MEM or input/output device IO
A signal that identifies access to C, W/R is a write/read identification signal, 1/PLL' When accessing memory MEM, instruction I or operand (data) P
A signal that identifies the
ta indicates data, respectively.

FIG. 3 (al is a diagram showing a sequence when the processor CPU writes data to the memory MEM, and fb in FIG. 3 is a diagram showing a sequence when the processor CPU reads data from the memory MEM.

FIG. 4 is a diagram showing the configuration of a program depacking device according to the present invention.

In the figure, CTL is a control circuit, RAM is a random access memory, ST-MAT is a first address comparison circuit, and B
L-MAT is a second address comparison circuit, SP-MAT is a third address comparison circuit, FF is a flip-flop circuit, G1, G2, and G3 are AND gates, RV is an amplifier, and BLM.

STA, SPA, DSP, and DPA are switches, respectively.
SEL is a selection circuit, and L is an indicator lamp.

The switch BLM is a switch for setting the address of the memory to be checked (for example, 6 units), and the switch STA is a switch for setting the check start address of the program to be checked (for example, 16 units), The switch SPA is a switch for setting the check end address of the program to be checked (for example, 16 units), the switch DSP is a switch that is pressed when you want to view the contents of the random access memory RAM from the outside, and the switch DPA is a switch that is pressed when you want to view the contents of the random access memory RAM from the outside. A switch (for example, 1) to set the memory address to be checked at that time.
0i position).

The present invention will be described in detail below with reference to the drawings.

The program depacking device P'DBG according to the present invention attempts to find a memory location that is destroyed while running a program to be tested, and as shown in FIG. 1, the program depacking device P'DBG The system
Used by connecting to bus 5BUS, system bus 5B
The US is configured as shown in FIG.

When the program to be tested runs, data is exchanged between the processor CPU and the memory MEM.
Address S identification signal 1/P, identification signal W/R1 identification signal M, EM/IO, bus access signal REQ, and response signal ACK are output to corresponding buses, respectively.

For example, when writing data from the processor CPU to the memory MEM, as shown in FIG.
Signal MEM/10 for identifying access to M or input/output device IOC, write/read identification signal W/R, signal 1 for identifying instruction I or operand (data) P when accessing memory MEM. /
Five types of information are output to each bus: P, an address indicating which address in the memory MEM to write to, and data Data, and then a bus access signal R is output.
EQ is output to the corresponding bus, and when the above operation is considered completed, a response signal ACK is output to the corresponding bus.

Also, when the processor CPU reads data from the memory MEM, all information is similarly output to the corresponding bus, as shown in FIG. 3(b).

The program depacking device PDBG according to the invention is branch-connected to such a bus.

The details of the program depacking device PDBG according to the present invention will be explained below with reference to FIG.

First, set the address to be checked in the program to be tested.

That is, the check start address is set by switch STA,
The check end address is set by the switch SPA, and the address of the memory to be checked is set by the switch BLM.

A program to be tested under the above conditions is loaded into the processor CPU shown in FIG. 1, and the program is run.

When the program runs, the first address comparison circuit ST-M
At the same time, the access signal to the memory MEM is applied to the control circuit C'TL, and the t2 signal is outputted, and the data 1 is output.
- Flip-flop circuit FF via G2F is set.

Next, when a command to input/output an address that matches the address set in the second address comparison circuit BL-MAT comes, the second address comparison circuit BL-MAT outputs an output signal and also outputs a bus access signal. REQ is control circuit CT
When the t1 signal is output by applying the t1 signal to L, the gate 1=G1 opens, outputs a write enable signal (WE), and writes the data at that time into the random access memory RAM.

When the program progresses further and reaches the set end address, the third address comparison circuit SP-MAT outputs a match output, and similarly passes through the gate G3 to the flip-flop circuit F.
Since F is reset, random access memory RA
Writing to M is stopped.

All the data input and output to the specified address between the check start address and end address set in this way will be randomly generated.
Since the information is written to the access memory RAM, using this material it is easier to find faults in the program than in the past.

The switches DPA, DSP, and selection circuit SEL are operating units used when viewing the contents of the random access memory RAM.

(f) Effects of the invention As explained in detail above, according to the present invention, the program
This has a great effect in that it is possible to easily find the location of memory corruption that occurred during depacking.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram illustrating one embodiment of a system bus according to the present invention. (al in FIG. 3 is a diagram showing a sequence when the processor CPU writes data to the memory MEM, and (bl in FIG. 3 is a diagram showing a sequence when the processor CPU reads data from the memory MEM. Fig. 4 is a diagram showing the configuration of the program depacking device according to the present invention.

Claims (1)

[Claims] A system having a processor and a memory, which receives at least address information and write data information among signals for accessing the memory from the processor, and further comprises a first address comparison circuit, a second address comparison circuit, and a third address. A program comprising a comparison circuit, inputting all or part of the address information to one input terminal of the three address comparison circuits and checking the other input terminal of the first address comparison circuit. Input the check start address, input the address of the memory to be checked into the other input terminal of the second address comparison circuit, and input the address of the memory to be checked into the other input terminal of the third address comparison circuit. Input the check end address, and after the first address comparison circuit matches, the second address comparison circuit writes the write data information of the address information that matches according to the address information. A program depacking device that writes to a random access memory and stops the write operation when the third address comparison circuit matches.