JPH03126147A - Test system for external storage device - Google Patents

Abstract

PURPOSE:To save a memory and to shorten a test time by suppressing write of check bits to write only data at the time of reading out data written in an external storage device to write it in the test data area of the memory and detecting data error at the time of reading out data from the test data area by a processor. CONSTITUTION:Data to be written in an external storage device 12 is generated in a test data area of a memory means 13 by a processor 11 and is written in the external storage device 12; and when written data is read out and is written in the test data area 21 of the memory means 15, write of data bits is suppressed by a suppressing means 17 and only data is written in a data part 14 of the memory means 13. When the processor 11 reads out the test data area 21 of the memory means 13, data error is detected in an error detecting means 16 by noncoincidence between the data part 14 of the memory means 13 and a check bit part 15 in the case of abnormality of data. The external storage device 12 is tested in this manner. Since it is sufficient if one test data area 21 is reserved, the memory is saved and the test time is shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding a test method for an external storage device of an information processing device, it is an object of the present invention to provide a test method for an external storage device that can save memory and shorten test time. A processor for executing a program, a memory means having a data section and a check bit section, an error detection means for generating a check bit when writing data to the memory means and detecting a data error when reading data, and an external storage. In the information processing apparatus equipped with the above-mentioned device, an inhibiting means for inhibiting writing of a check bit is provided between the error detecting means and the memory means, and the data written in the test data area of the memory means is transferred to the external storage device. After writing data in the external storage device to the test data area, writing of the check bit is inhibited and only data is written, and when reading data from the test data area, the error detection means detects an error. It was configured to do so.

[Industrial Field of Application] The present invention relates to a test method for an external storage device of an information processing device.

In an information processing device equipped with an external storage device, data is read from the test data area of the memory, written to the test area of the external storage device, read the written data from the test area of the external storage device, and compared the data. and test the external storage device. In this case, it is necessary to perform the test in a short time.

[Prior Art] As a conventional external storage device testing method, there is one shown in FIG. 5, for example.

In FIG. 5, 1 is a processor that executes a program, 2 is an external storage device to be tested, and 3 is a memory having a data section 4 and a check bit section 5. Processor 1 , external storage device 2 and memory 3 are connected via data bus 6 , and memory error detection circuit 7 is provided between memory 3 and processor 1 and external storage device 2 . The memory error detection circuit 7 generates check pits such as ECC when writing data to the memory 3, and detects errors using the check pits when reading data from the memory 3.

As shown in FIG. 6(A), the processor 1 first creates data to be written to the external storage device 2 in the write data area 8 of the memory 3. Next, as shown in FIG. 6(B), the processor 1 instructs the external storage device 2 to read data from the write data area 8 of the memory 3. In this way, data is written to the external storage device 2.

Next, as shown in FIG. 6C, the processor 1 instructs the external storage device 2 to read data from the read data area 9 of the memory 3, which has the same size as the write data area 8. In this way, data is written into the read data area 9 of the memory 3.

Next, as shown in FIG. 6(D), the processor 1 compares the data in the write data area 8 and the data in the read data area 9 of the memory 3 to test the external storage device 2. If the data do not match, it is determined that there is an abnormality in the external storage device 2.

[Problems to be Solved by the Invention] However, in such a test method for external storage devices, two areas are required in the memory, a write data area and a read data area, and the memory usage area is large. In addition, since data must be read from the write data area and the read data area and compared, there is a problem that testing takes time.

The present invention has been made in view of these conventional problems, and it is an object of the present invention to provide a test method for external storage devices that can save memory and shorten test time. The purpose is

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 11 is a processor that executes a program, 13 is a memory means having a data section 14 and a check bit section 15, and 16 is a memory means 13 that generates check pits when writing data and detects data errors when reading data. 12 is an external storage device; 17 is the error detection means 16 and the memory means 13;
This is a suppressing means provided between the check pit and the check pit.

[Operation] In the present invention, data to be written to the external storage device by the processor is created in the test data area of the memory means, written to the external storage device from the test data area of the memory means, and the written data is read and written to the memory means. When writing to the test data area of the test data area, the inhibiting means inhibits writing of data bits, and only data is written to the data section of the memory means. When the processor reads out the test data area of the memory means, if the data is abnormal, the error detection means detects a data error due to mismatch between the data section and the check pit section of the memory means. In this way, the external storage device is tested.

Therefore, since it is only necessary to secure one test data area, the area used by the memory means is reduced, resulting in memory savings.Furthermore, since testing can be performed by reading out one test data area, Test time can be shortened.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 to 4 are diagrams showing one embodiment of the present invention.

In FIG. 2, 11 is a processor that executes a program, 12 is an external storage device to be tested, and 13 is a memory (13) having a data section 14 and a check pit section 15.
memory means). Data is stored in a data section 14 of the memory 13, and check bits generated by a memory error detection circuit (error detection means) 16 are stored in a check pit section 15. The memory error detection circuit 16 generates a check bit and writes it into the memory 13 when writing data to the memory 13, and detects a data error using the check bit when reading data from the memory 13. Reference numeral 17 denotes a check pit write inhibiting circuit as a inhibiting means. The check bit writing inhibiting circuit 17 is provided between the memory error detecting circuit 16 and the memory 13, and reads data from the external storage device 12 and writes it into the memory 13. At this time, writing of the check bit is inhibited according to an instruction from the processor 11. Therefore, only data is written into the data section 14.

18 is a data bus, and the processor 11, external storage device 12, and memory 13 are connected to each other via the data bus 18.

Next, the check bit write inhibit circuit 17 will be explained based on FIG.

In FIG. 3, 14 is the data section of memory l] 13, and 15 is
is a check pit portion of the memory 13. Data section 14
Data is written in by the write enable signal (WTEN), and the AND circuit 19 is written in the check pit section 15.
A check bit is written by a write enable signal (WTEN) inputted to the memory, and writing of the check bit is inhibited by an inhibit signal (WTINH). The inhibit signal (WTINH) is stored in the register 20 according to instructions from the processor 11. Therefore, AND circuit 19 and register 20 constitute check bit write inhibit circuit 17 as a whole.

Next, the operation will be explained.

FIG. 4 (A-D) is an explanatory diagram of the operation of the present invention.

In FIG. 4A, first, the processor 11 creates data to be written to the external storage device 12 in the test data area 21 of the memory 13.

Next, as shown in FIG. 4(B), the processor 11 instructs the external storage device 12 to write data in the test data area 21 of the memory 13. In this way, the data in the test data area 21 is read and written to the test area of the external storage device 12.

Next, as shown in FIG. 4(C), the processor 11 issues an instruction to the check pit write inhibit circuit 17 to inhibit check pit write, and reads data from the test area to the external storage device 12. memory 13
An instruction to write to the test data area 21 is issued.

In this way, only data from the test area of the external storage device 12 is written to the data section 14 of the test data area 21 of the memory 13, and writing of check bits is inhibited.

Next, as shown in FIG. 4(D), the processor 11 sequentially reads the test data area 21 of the memory 13. In this case, if the read data from the external storage device 12 is abnormal, when the processor 11 reads the address on the test data area 21 of the memory 13, the memory 13
Since the data section 14 and check bit section 15 within the memory do not correspond, the memory error detection circuit 16 detects a data error. In this way, the external storage device 12 can be tested.

In the conventional example, it was necessary to secure two areas, a write data area and a read data area, but in this embodiment, it is sufficient to secure one test data area 21.
The area used in the memory 13 is reduced, and memory can be saved.

In addition, in the conventional example, two areas were read and compared, which took a long time to test, but in this embodiment, it is only necessary to read one test data area 21, so the test time can be shortened. Can be done.

[Effects of the Invention] As explained above, according to the present invention, data can be written from the test data area of the memory to the external storage device,
When reading the data written to the external storage device and writing it to the test data area of the memory, writing of the check bit is suppressed and only the data is written, and when the processor reads from the test data area, a data error is detected. Since it is sufficient to secure one test data area, the amount of memory used can be reduced, resulting in memory savings. Furthermore, since a test can be performed by reading out one test data area, the test time can be shortened.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing an embodiment of the invention, Fig. 3 is a diagram showing a check pit write inhibit circuit, Fig. 4 is a diagram explaining the operation, and Fig. 5 is a diagram showing an embodiment of the present invention. FIG. 6 is an explanatory diagram of the operation of the conventional example. In the figure, 11... Processor, 12... External storage device, 13... Memory (memory means), 14... Data section, 15... Check bit section, 16... Memory error detection circuit (error detection means),
17...Check pit write suppression circuit (suppression means)
, 18...Data bus, 19...AND circuit, 20...Register, 21...Test data area.

Claims (1)

[Claims] A processor (11) that executes a program; a memory means (13) having a data section (14) and a check bit section (15); In an information processing device including an error detection means (16) for detecting an error and an external storage device (12), writing of a check bit between the error detection means (16) and the memory means (13) is inhibited. A test data area (2) of the memory means (13) is provided.
After writing the data written in 1) to the external storage device (12), when writing the data of the external storage device (12) to the test data area (21), write of the check bit is inhibited and the data is 1. A test method for an external storage device, characterized in that the error detection means (16) detects an error when only writing data and reading data from the test data area (21).