JPS60549A - Memory testing system - Google Patents

Memory testing system

Info

Publication number
JPS60549A
JPS60549A JP58107163A JP10716383A JPS60549A JP S60549 A JPS60549 A JP S60549A JP 58107163 A JP58107163 A JP 58107163A JP 10716383 A JP10716383 A JP 10716383A JP S60549 A JPS60549 A JP S60549A
Authority
JP
Japan
Prior art keywords
address
memory
data
test
pattern data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58107163A
Other languages
Japanese (ja)
Inventor
Masami Murayama
雅美 村山
Toshio Kunigami
国上　俊雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58107163A priority Critical patent/JPS60549A/en
Publication of JPS60549A publication Critical patent/JPS60549A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To put efficiently a memory to a test, by temporatily saving the stored content of an address of the memory to be tested in another memory, and returning the content to the original address after the test is terminated. CONSTITUTION:When the (n) address of a memory MEM is assigned by means of a microprocessor MPU through a selector SEL2, the content of the (n) address is transferred to a prescribed address of another memory and then a testing pattern data is written in the (n) address. When the writing is completed, the written testing pattern data is immediately read out and compared with testing pattern data. The compared result is outputted to an output device. After the comparison, the data transferred to a specific address of another memory is returned to the (n) address, and thus, the test is terminated.

Description

【発明の詳細な説明】 （ａ）６発明の技術分野 本発明はデータ処理装置のメモリの試験方式に係り、特
にオン・ライン処理中にも実施出来るメモリ試験方式に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) 6 Technical Field of the Invention The present invention relates to a memory testing method for a data processing device, and particularly to a memory testing method that can be performed even during online processing.

（ｂ）、従来技術の問題点 従来技術に依るとデータ処理装置のメモリの試験方法は
データにパリティ・ビットを付加して試験するメモリに
書込み、此れを読み出した時パリテ、（・チェックをし
ていた。(b) Problems with the prior art According to the prior art, the method of testing the memory of a data processing device is to add a parity bit to the data and write it into the memory to be tested, and when reading this out, the parity bit is checked. Was.

然し記憶しようとするデータが例えば音声信号、画像信
号等の場合には、パリティ・チェ７りに一回程度不合格
でも元のデータへ再生するのに支障を来すことはない。However, if the data to be stored is, for example, an audio signal or an image signal, even if the parity check fails once or so, there will be no problem in reproducing the original data.

即ち音声信号、画像信号等の場合には、一連のデータの
間には関連性・連続性があり、板金１ビットのデータが
不正確でありでもデータ全体の掌握には不都合を与える
ことはないので、従来のパリティ・チェック方式では、
チェック・ビットの分だけ余分にメモリを使用しなけれ
ばならないと云う欠点がある。In other words, in the case of audio signals, image signals, etc., there is a relationship and continuity between a series of data, and even if one bit of sheet metal data is inaccurate, it will not cause any problems in understanding the entire data. Therefore, in the conventional parity check method,
The disadvantage is that extra memory must be used for the check bits.

（Ｃ）９発明の目的 本発明の目的は従来技術の有する上記の欠点を除去し、
より効果的なメモリの試験方式を提供することである。(C)9 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art;
The objective is to provide a more effective memory testing method.

（ｄ）１発明の構成 上記の目的は本発明によれば、音声信号、画像信号等の
データを記憶するメモリの試験方式に於いて、試験しよ
うとする前記メモリの任意のアドレスの記憶内容を一時
別のメモリに退避させ、前記アドレスに所定のデータを
書き込み後読み出して得られたデータと前記所定のデー
タを比較し、前記比較動作終了後、前記別のメモリに退
避させたデータを元に戻すことを特徴とするメモリ試験
方式を提供することにより達成される。(d) 1 Structure of the Invention According to the present invention, in a test method for a memory that stores data such as an audio signal or an image signal, the storage content of an arbitrary address of the memory to be tested is Temporarily save it to another memory, write predetermined data to the address, read it out, compare the obtained data with the predetermined data, and after the comparison operation is completed, based on the data saved to the another memory. This is achieved by providing a memory testing method that is characterized by

（ｅ）０発明の実施例 図は本発明の一実施例を示す図である。(e) 0 Examples of the invention The figure shows an embodiment of the present invention.

図中、ＭＥＭは試験対象となるメモリ、ＭＰＵはマイク
ロ・プロセッサ、ＳＥＬ　１．５ＥＬ２は夫々セレクタ
、ＢＵＳはバスである。In the figure, MEM is a memory to be tested, MPU is a microprocessor, SEL 1.5EL2 are selectors, and BUS is a bus.

尚セレクタＳＥＬ　１に入力するＨＡＲＤ　−ＤＡＴＡ
は此のマイクロ・プロセッサＭＰＵ系の外部から来るデ
ータを示し、セレクタ５ＥＬ２に入力するＨＡＲＤ　−
ＡＤＤは此のマイクロ・プロセンサＭＰＵ系の外部の機
器のアドレス、Ａ−ＢＵＳはアドレス・バスを示す。In addition, HARD-DATA input to selector SEL 1
indicates data coming from outside this microprocessor MPU system, which is input to selector 5EL2.
ADD indicates the address of a device external to this micro-processor MPU system, and A-BUS indicates an address bus.

以下図に従って本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

図に示すマイクロ・プロセッサＭＰＵ系は外部の各種機
器と連動して規定されたオン・ラインの仕事をしている
。オン・ライン・プログラムの中に一定時間毎にマイク
ロ・プロセッサに割り込みがかかり、以下に述べる試験
プログラムに移行し、所定数のアドレスを試験した復元
に戻す。The microprocessor MPU system shown in the figure performs prescribed online work in conjunction with various external devices. During the on-line program, the microprocessor is interrupted at regular intervals, transitions to the test program described below, and returns a predetermined number of addresses to the tested restoration state.

今メモリＭＥＭＯ中の試験しようとするアドレスをｎと
する。Let n be the address to be tested in the memory MEMO.

最初マイクロ・プロセッサＭＰＵにより、セレクタ５Ｅ
Ｌ２を経由してメモリＭＥＭのｎアドレスを指定し、ア
ドレスｎの内容を別のメモリの所定のアドレス（又は特
定のレジスタ）に移し、次にアドレスｎに試験パターン
・データを書込む。Initially, the microprocessor MPU selector 5E
Specify n address of memory MEM via L2, move the contents of address n to a predetermined address (or specific register) of another memory, and then write test pattern data to address n.

此の試験パターン・データの一例は下記の様なデータを
組み合わせて使用する。An example of this test pattern data is a combination of the following data.

ｉ）オール０．ｉｉ）オール１．１ｉｉ）０１０１書込
みを完了したならば、直ちに此れを読み出し、読み出さ
れたデータと前記試験パターン・データをマイクロ・プ
ロセッサＭＰＵに於いて比較し、一致していれば合格、
不一致ならば不合格とし、出力装置に此の結果を出力す
る。i) All 0. ii) Once all 1.1ii) 0101 writing is completed, read it immediately, compare the read data and the test pattern data in the microprocessor MPU, and if they match, pass.
If they do not match, it is judged as a failure and the result is output to the output device.

比較動作の終了後、再び別のメモリの所定のアドレス（
又は特定のレジスタ）に移してあったデータをｎアドレ
スに戻し、ｎアドレスの試験を終わり、次のｆｉ＋ｌア
ドレスの試験に移る。此の様にしてメモリＭＥＭの総て
のアドレスについて試験することが出来る。After the comparison operation is completed, the predetermined address (
or a specific register) is returned to the n address, the test of the n address is completed, and the next test of the fi+l address is started. In this way, all addresses of the memory MEM can be tested.

（ｆ）０発明の効果 以上詳細に説明した様に本発明によれば、オン・ライン
処理を実施しながらより効率的なメモリの試験を実施出
来ると云う大きい効果がある。(f) Effects of the Invention As described in detail above, the present invention has the great effect of being able to perform more efficient memory tests while performing online processing.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例を示すブロフク図である。 図中、ＭＥＭは試験対象となるメモリ、ＭＰＵはマイク
ロ・プロセッサ、５ＥＬ１．５ＥＬ２は夫々セレクタ、
ＢＵＳはバスである。The figure is a diagram showing one embodiment of the present invention. In the figure, MEM is the memory to be tested, MPU is the microprocessor, 5EL1 and 5EL2 are the selectors, respectively.
BUS is a bus.

Claims (1)

【特許請求の範囲】[Claims] 音声信号、画像信号等のデータを記憶するメモリの試験
方式に於いて、試験しようとする前記メモリの任意のア
ドレスの記憶内容を一時別のメモリに退避させ、前記ア
ドレスに所定のデータを書き込み後読み出して得られた
データと前記所定のデータを比較し、前記比較動作終了
後、前記別のメモリに退避させたデータを元に戻すこと
を特徴とするメモリ試験方式。In a test method for memory that stores data such as audio signals and image signals, the contents of an arbitrary address of the memory to be tested are temporarily saved to another memory, and after writing specified data to the address. A memory test method characterized in that the data obtained by reading and the predetermined data are compared, and after the comparison operation is completed, the data saved in the other memory is restored.
JP58107163A 1983-06-15 1983-06-15 Memory testing system Pending JPS60549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107163A JPS60549A (en) 1983-06-15 1983-06-15 Memory testing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107163A JPS60549A (en) 1983-06-15 1983-06-15 Memory testing system

Publications (1)

Publication Number Publication Date
JPS60549A true JPS60549A (en) 1985-01-05

Family

ID=14452082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107163A Pending JPS60549A (en) 1983-06-15 1983-06-15 Memory testing system

Country Status (1)

Country Link
JP (1) JPS60549A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390060U (en) * 1986-11-28 1988-06-11
JPH0532647U (en) * 1991-10-08 1993-04-30 ワイケイケイアーキテクチユラルプロダクツ株式会社 Locking device for window with built-in blind

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6390060U (en) * 1986-11-28 1988-06-11
JPH0532647U (en) * 1991-10-08 1993-04-30 ワイケイケイアーキテクチユラルプロダクツ株式会社 Locking device for window with built-in blind
JP2536463Y2 (en) * 1991-10-08 1997-05-21 ワイケイケイアーキテクチュラルプロダクツ株式会社 Blind built-in sash window locking device

Similar Documents

Publication Publication Date Title
US4368532A (en) Memory checking method
JPS60549A (en) Memory testing system
JPS6041150A (en) Storage device control system
JPS59197946A (en) Memory device
JPH0528058A (en) Memory address bus test system
JPH11288598A (en) Test device for semiconductor memory
JPS59153247A (en) Debugging device
JPS59226955A (en) Program debug device
JPS59163653A (en) Debug device
JPH02302855A (en) Memory control system
JPS63285642A (en) Microprocessor control system
JPH09198274A (en) Method for testing device having processor and ram
JPH01197860A (en) Memory fault detecting circuit
JPS6130356B2 (en)
JPH04106647A (en) Memory diagnostic system
JPS63136238A (en) Microprogram control device
JPH05241900A (en) Program operation confirmation system of computer
JPS617947A (en) Control storage device
JPH0573437A (en) Memory parity circuit
JPH02245847A (en) Memory test system
JPS60103597A (en) System for storing function test result in ic memory test system
JPS62272164A (en) Testing equipment for semiconductor memory
JPH03126147A (en) Test system for external storage device
JPH02151940A (en) Trace memory system
JPS58182761A (en) Data checking system