JPS617947A - Control storage device - Google Patents

Abstract

PURPOSE:To secure the reliability of a loaded data by comparing a data read out of a read only memory circuit, with a data which is read out after writing its data in a read/write capable memory. CONSTITUTION:When a load request signal is inputted, a read only memory circuit 3 is brought to access by address information from an address register 2 in accordance with the instruction of an address controlling circuit 1, and a micro- word is outputted, and written in a read/write capable memory circuit 4 through a register 5. The written micro-word is read out again and inputted to a comparing circuit 7 through a register 6. The circuit 7 compares the data from the circuit 3 and the circuit 4, sends out a coincidence signal when they coincide with each other, and reports it to the circuit 1. The circuit 1 brings the register 2 to an increment by ''1'', and repeats it. When it is ended, it is reported through a signal line 56 by a load end signal that a load operation to the circuit 4 from the circuit 3 is ended normally.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control storage device for a microprogram control device, and more particularly to checking when a microprogram is loaded.

(Prior Art) In a microprogram control device, when a microprogram is stored in a read/write dedicated memory circuit and used by being loaded into a read/write memory circuit, the conventional method is to store the microprogram in a read/write memory circuit. The microwords are simply loaded sequentially from the memory circuit to the read/write memory circuit, but the validity of the microwords cannot be checked during loading, and is checked by parity check after loading.

(Problem to be solved by the invention) Therefore, once an error occurs, there is no guarantee that the microprogram is correctly loaded into the readable/writable memory circuit, so it is difficult to determine what caused the error. The drawback was that it was very difficult to distinguish.

For example, if multiple bits are erroneous at the same time, conventional parity checking methods cannot detect this, and even if a single bit is erroneous, it is difficult to determine which bit is erroneous. There were drawbacks.

It is an object of the present invention to provide a method in which, during loading of a microprogram to be loaded into a read/write memory circuit from a read-only memory circuit, a microword read from the read-only memory circuit and this microword are The above disadvantages are eliminated by adding a check function to check whether the data matches what is read out again after being written into the writable memory circuit. An object of the present invention is to provide a control storage device for a microprogram control device that guarantees the reliability of microprograms.

SUMMARY OF THE INVENTION A control storage device according to the invention includes a read-only memory path, a first register, a read/write memory circuit, an address register, an address control circuit, and a second register. It is a turtle that is equipped with a register, a comparison circuit, and a reporting means.

The read-only memory circuit is for storing microprograms.

The first register is for temporarily storing microwords read from the read-only memory circuit.

The read/write memory circuit is a turtle for writing and holding microwords sequentially starting from the first register.

The address register is a tortoise that provides addresses to read/write memory circuits as well as read-only memory circuits.

The address control circuit is for controlling the address register to increment the address.

The second register is for temporarily storing microwords read from the read/write memory circuit.

The comparison circuit is for comparing the contents of the first register and the contents of the second register with each other.

The reporting means is for sending the comparison result by the comparison circuit to the address control circuit.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a control storage device according to the present invention. In FIG. 1, 1 is an address control circuit, 2 is an address register, 6 is a read-only memory circuit, 4 is a read/write memory circuit, 5 is a first register, 6 is a second register, and 7 is a comparison circuit. It is.

In FIG. 1, when a load request signal is input through the signal line 50 when the power is turned on, the address control circuit 1
sends an address register clear signal onto signal line 51 to clear address register 2. The read-only memory circuit 6 storing the microprogram is accessed by the address information outputted from the address register 2 onto the signal line 100, and a microword is outputted onto the data signal line 101. The output microword is stored in the first register 5 and further written to the data path 4. The microword written to the read/write memory circuit 4 is read out from the read/write memory circuit 4 again,
The signal is stored in the second register 6 through the data signal line 103.

Thereafter, the microword stored in the first register 5 is input to the comparator circuit 7 through the data signal line 102.
The microword stored in the second register 6 is the data signal I! The signal is input to the comparator circuit 7 through 1104. If the microword in the first register 5 and the microword in the second register 60 match, the comparison circuit 7 sends a match signal onto the signal line 54 and reports it to the address control circuit 1.

When a match signal arrives via signal @54, address control circuit 1 sends an address increment signal on signal line 52 to increment the contents of address register 2 by one. As a result, the above operation is repeated using the set address value. When the address value of the address register 2 reaches the end value, a end signal is sent onto the signal line 53 and is reported to the address control circuit 1. When the end signal arrives via the signal line 53, the address control circuit 1 reports that the signal line loading operation has been completed normally.

However, if the comparison circuit 7 detects a mismatch midway through, the comparison circuit 7 connects the address control circuit 1 to the address control circuit 1 via the signal line 54.
Instead, it sends an error signal on signal line 55 to abort the loading operation, thereby reporting an error.

(Effects of the Invention) As explained above, the present invention writes the data read from the read-only memory circuit and the data in the read/write memory circuit in the process of loading a microprogram, and then reads the data again. The reliability of the loaded data is guaranteed by comparing both data with the data obtained by

That is, according to the present invention, when an error occurs, the number of erroneous bits and the bit position can be easily determined by displaying and comparing the microwords stored in a pair of registers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a control storage device according to the present invention. 1...Address control circuit 2...-7Dress register 6...Read 9-only memory circuit 4...Memory circuit that can fail/damage 5.6.Conflict register 7.Conflict comparison circuit

Claims (1)

[Claims] a read-only memory circuit for storing a microprogram; a first register for temporarily storing microwords read from said read-only memory circuit; and a first register for temporarily storing said microwords from said first register. a read/write memory circuit for writing and holding; an address register for providing addresses to the read/write memory circuit and the read-only memory circuit; and controlling the address register to provide the address. an address control circuit for incrementing the microword; a second register for temporarily storing the microword read from the read/write memory circuit; and the contents of the first register and the second register. 1. A control storage device comprising: a comparison circuit for comparing the contents of the addresses, and a reporting means for sending a comparison result by the comparison circuit to the address control circuit.