JPH01189745A - Memory write system - Google Patents

Abstract

PURPOSE:To evade the destruction of data by returning the data to the one before write is performed even when an error is detected after the write of the data is completed in a memory erroneous write recovery system. CONSTITUTION:To perform memory write, a signal is added on each of a command signal line 101, an address signal line 102, and a data signal line 103, respectively, and is sent to a memory access circuit 2, and a received address is sent from the means 2 to an address signal line 202, and a write effective signal 201 is turned OFF, and address data is sent from a memory 1 to a data output line 303. At this timing, a retreat signal 301 is outputted from the circuit 2, and is added on a retreat register 3, and also, the signal of the output line 303 is retreated, then, the effective signal 201 is turned ON. By turning ON the signal 201, the memory 1 writes the data from a write data line on the address designated by the signal line 202, and the circuit 2 completes the write by turning OFF the effective signal 201 again. At this time, when the error is generated, an error signal 504 is added on the circuit 2 as a write back signal 401 via a recovery control circuit 4, then, the error is corrected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory recovery method when a memory write error occurs, and in particular, a memory error recovery method when a check result for a memory write is obtained after the end of the memory write. Regarding the method.

[Conventional technology]

Conventionally, commands and addresses sent to memory to access memory were used as a method to prevent memory write errors.
Data parity checks and command validity checks are performed, and if an error exists, memory writing is inhibited to prevent memory contents from being destroyed. The means for accessing was duplicated and a comparison was made to check whether there were any errors in the memory write requested by the means.

[Problem that the invention seeks to solve]

In the conventional method for dealing with erroneous memory writes described above, in the case of the parity check method, even if the means attempting to write to memory sends an incorrect command, address, or data, it is not possible to check whether the command is a defined command or has correct parity. If there was, the error could not be detected during the parity check, allowing an erroneous memory write, and even if it was later detected that there was an error in the memory write, the memory data before the write was lost. .

Furthermore, even in a method of detecting erroneous memory writing by duplicating the means for accessing the memory, if an error signal arrives at the memory after the memory writing is completed, it is not possible to restore the data before writing.

In many cases, when an error occurs and an attempt is made to retry the instruction, the contents of the memory have been rewritten, making it impossible to retry the instruction.

[Means for solving problems]

In a device that has a memory and writes data to the memory, there is a memory, an address to which the memory is written when data is written to the memory, and a save register that stores the data that was held at that address before the memory was written. , accepts a memory write request from a means attempting to write to memory, executes the requested memory write,
In addition, when a write-back signal is input, a memory access control circuit that takes the save address and save data stored in the save register and writes the save data to the memory address indicated by the save address, and a request is made to the memory access control circuit. When it is discovered that there is an error in memory writing, the error signal from the means that discovered the error is input and a write-back signal is sent to the memory access control circuit.Repair control P('-・-4, . i + circuit.

〔Example〕

Next, the present invention will be explained with reference to simple drawings.

FIG. 1 is a 7772 diagram of an embodiment of the present invention.

The memory erroneous write repair method shown in FIG. 1 includes a memory 1, a memory access control circuit 2, a save register 3, and a repair control circuit 4.

Next, the operation of one embodiment of the present invention will be explained. Since the case of memory read is not directly related to the present invention, the case of memory write will be explained here. A means (not shown) for performing memory writing outputs a command representing memory writing to the command signal line 101, a memory address to the address signal line 102, and write data to the data signal line 103. and sends it to the memory access control circuit 2. Upon receiving these signals, the memory access control circuit 2 first outputs the address sent from the address signal line 102 to the memory address signal line 202, and turns off the write enable signal 201. Then, memory 1 receives the memory address signal line 202.
Read the data at the address indicated by the data signal line 30.
Output to 3.

At this timing, the memory access control circuit 1 outputs the save signal 301, and the save register 3 receives this and converts the address output to the memory address signal line 202 and the data output to the read data signal line 303 to the save address. , and store it as saved data. After that, the memory access control circuit 2 outputs the write data sent from the data signal line 103 to the write data signal line 203,
Turn on the write enable signal 201. Write valid signal 2
01 is turned on, the memory l writes the write data signal line 2 to the address indicated by the memory address signal line 202.
Write the data sent from 03. After that, the memory access control circuit 2 turns off the write enable signal 201,
If no error is detected in memory writing, the writing operation ends.

If some kind of error is detected in the memory write operation after the memory write operation is completed, for example, if the means for writing to memory are duplicated and memory 1 is writing data, two means If an error is detected in the requested memory write by comparing the operations between When an attempt is made to retry the instruction after detecting an error, the means that detected the error outputs an error signal 504. Upon receiving this, the modification control circuit 4 outputs a write-back signal 401 to the memory access control circuit 2. Upon receiving the write-back signal 401, the memory access control circuit 2 transfers the save address stored in the save register 3 from the save address signal line 402 and the save data from the save data signal line 403.
from memory address lines 202., respectively. It is output to the write data signal line 203. Then, the write enable signal 201 is turned on and the save data is written to the address of the memory 1 indicated by the save address.

This restores the data before memory writing, and prevents memory data from being destroyed due to erroneous memory writing.

〔Effect of the invention〕

As explained above, the memory write error recovery method of the present invention can restore the data before the write even if it is detected that there was an error in the memory write after the memory write is completed. It is possible to prevent data from being destroyed due to erroneous memory writing, which has the effect of increasing the probability that the instruction can be retried even if an error occurs during execution of a software instruction that involves memory writing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Memory, 2... Memory access control circuit, 3... Save register, 4...
・Repair control circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] A device having a memory and writing data to the memory, comprising: a memory, an address to which the memory is written when data is written to the memory, and an address held before the memory is written to the address. A save register for storing data, a memory write request from a means attempting to write to the memory, executes the requested memory write, and when a write-back signal is input, the save address stored in the save register is a memory access control circuit that takes in saved data and writes the saved data to a memory address indicated by the saved address; and means for discovering a memory write error requested to the memory access control circuit when it is discovered that the error exists. and a repair control circuit that inputs an error signal coming from the memory access control circuit and sends a write-back signal to the memory access control circuit.