JPH03290745A - Memory error detecting/correcting method - Google Patents

Abstract

PURPOSE:To correct a memory error with application of a parity check system by usually performing the horizontal parity check to the memory read data and then carrying out the vertical parity check only when a parity error is detected. CONSTITUTION:A memory 11 is logically divided into blocks BL0 - BLN-1 in the address direction, and a parity bit is added to each block in both horizontal and vertical directions. In a read access state of the memory 11, the horizontal parity check is carried out. If a parity error is detected in the horizontal parity check, the vertical parity check is carried out to the corresponding block. If a parity error is detected in the vertical parity check, the bit position shows a position of an error bit in the word data received a memory read access. Thus the error is easily corrected on the basis of the parity check.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) This invention relates to an improved error detection and correction method for memory.

(Prior art) As methods for detecting errors in memory, there are conventionally two methods: ■ A method in which a parity bit is added to each word of data and a parity check is performed to perform only error detection, and ■ A method for error detection and correction (ECC). A method is known in which a check bit is added to detect and correct errors of one bit and errors of two or more bits.

(Problem to be Solved by the Invention) The conventional error detection methods described above have the disadvantage that, for example, method (■) only detects errors but cannot correct errors, whereas method (■) can correct 1-bit errors. However, the drawback was that the error detection and correction circuitry was complicated.

The present invention has been made in view of the above circumstances, and its purpose is to relate to a memory error detection/correction method that is based on parity checking and allows for easy error correction.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a memory in which a parity bit (first parity bit) is added horizontally (for each word data) into a plurality of blocks in the address direction. A parity bit (second parity bit) is added to each block in the vertical direction (for each bit position), and at the time of memory read access, a horizontal parity check (first parity bit) is performed on the read word data. If a parity error is detected, a vertical parity check (second parity check) is performed for each bit position of the block where the corresponding word data exists, and an error is detected in the horizontal direction. This method is characterized in that the bit data at the bit position where an error occurred in the vertical direction is inverted and corrected among the word data where there was an error.

(Function) In this invention, the memory is logically divided into a plurality of blocks in the address direction (vertical direction), and parity bits are added to each block not only in the horizontal direction but also in the vertical direction. At the time of memory read access to such a memory, a horizontal parity check is performed as in the past.

If a parity error is detected in this horizontal parity check, then a vertical parity check of the corresponding block is performed. The bit position where a parity error is detected in this vertical parity check indicates the position of the error bit in the word data accessed for memory read access.

Therefore, error correction can be performed by inverting the bit data at the bit position where an error occurs in the vertical direction among the word data where an error occurs in the horizontal direction.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a data processing apparatus to which the present invention is applied. In the figure, numeral 11 is a 2 arm word x 8 bit (+1 parity pit) memory for storing various programs, data, etc. The memory 11 is addressed by an n+m bit memory address.

A parity bit is attached to each word data in the memory 11 as in the conventional case. That is, in the memory 11, one parity bit (
Horizontal parity bit) is added. Here, the value of the lower m bits is i (i-Q~M-1, where M-2"
) The parity bit added to the word data in the memory 11 indicated by the memory address (n 10 m bits) is represented by HPi. The memory 11 is logically divided into N equal parts (N-2'') in the address direction (vertical direction) and has N blocks BLo to BL of size M (that is, M words).
, is divided into. In this embodiment, each block BL, (j
-0 to N-1), one parity bit (vertical parity bit) is added for M bits in the vertical direction.

Here, the vertical parity bit of bit k (k-0 to k-7) of block BL is represented by VPk.

12 are parity bits VPo~■ of bits 0 to 7 of each block BLO-BLN-1.
Vertical parity bit memory (hereinafter referred to as ■P memory) for storing P7 in correspondence with the block address (upper n bits of the memory address) (specifying the corresponding block), 13 is a memory read access to the memory 11 This is a parity check circuit (hereinafter referred to as a PC circuit) that performs a parity check of memory read data read from the memory 11 by the following. The PC circuit 13 is designed to generate an interrupt signal INT to the CPU 14, which will be described below, when a parity error is detected. 1
4 is a CPU that controls the entire device. This CPU14
performs processing to update the vertical parity bit (VP bit) in the vP memory 12 at the time of memory write access to the memory 11, and performs error correction for memory data in which an error has been detected when an interrupt signal INT is generated from the PC circuit 13. It is designed to be processed.

FIG. 2 is a flowchart showing the procedure for vP bit update processing, and FIG. 3 is a flowchart showing the procedure for error correction processing.

Next, the operation of the configuration shown in FIG. 1 will be explained with reference to the flowcharts shown in FIGS. 2 and 3. Note that in this embodiment, an odd parity method is applied.

First, in an initial state where the memory 11 is all cleared to "0", the contents of the vP memory 12 are also all cleared to "0". When a memory write access request to the memory 11 is generated in such a state, the memory data at the memory write destination is read out prior to the memory write access (step 52 in FIG. 2). The CPU 14 performs an exclusive OR (hereinafter referred to as EXOR) for each bit 0 to 7 between the memory data read from the memory 11 at the memory write destination and the memory write data to be written to the memory 11 from now on. (Step 52 in Figure 2)
. The EXOR result for each bit indicates whether the corresponding bit is substantially rewritten by the memory write (in the case of "1") or not (in the case of "0").

Now, the upper n bits of the memory address for the memory 11, ie, the block address, are used as the address for the VP memory 12. As a result, the vertical parity bit V P o of the block to which the memory write destination belongs
'=V P 7 is read from the vP memory 12 . The CPU-U 14 uses the EXOR result for each bit 0 to 7 obtained in step S2 as mask data, and
Vertical parity bit v read from P memory 12
po-vp, the parity bit (VP bit) at the bit position where the EXOR result is “1” is inverted, and V
Write back to the original location in the P memory 12 (Step S in Figure 2)
3).

As a result, the vertical parity bit VPO-vp7 of the block to which the memory write destination belongs is updated to correspond to the vertical bit data of each bit of the memory 11 after the memory write of the same block.

Next, error correction processing when a parity error is detected during memory read access will be described.

First, a memory read access request to the memory 11 is generated, and the 8
Assume that bit memory data is read from memory 11. At this time, the horizontal parity bit HPI (0≦1≦M-1) attached to the memory data is also read out at the same time.

The PC circuit 13 uses the 8-bit memory data read from the memory 11 and its parity bit HPl,
A well-known parity check is performed, and if a parity error (in this case, there is an error in an odd numbered bit) is detected, an interrupt signal INT to the CPU 14 is generated.

The CPU 14 uses the PC circuit 13 during memory read access.
When receiving the interrupt signal INT from the memory 11,
The block to which the current memory address that caused the parity error belongs (hereinafter referred to as the current block) BL, (0≦j≦N
-1) is read (step 511 in FIG. 3) and held in an internal register (not shown) (step 512 in FIG. 3). Then CPU14
reads the memory data at the next address of the current block BL from the memory 11 (step 513 in FIG. 3).

Then, the CPU 14 performs EXOR for each corresponding bit between the memory data read in step 313 and the data held in the internal register (step S14 in FIG. 3).
, replaces the data held in the internal register with the EXOR result for each bit (step 515 in FIG. 3). The CPU 14 performs the processing of steps 513 to 515 on the current block B.
Repeat until the last memory data of L. Eventually, when the processing of the last memory data of the current block BL is completed, the data held in the internal register at that time indicates the vertical parity pit for each bit position for the memory data group of the current block BL. become.

When the CPU 14 determines that processing has been completed for the last memory data of the current block BL (step 516 in FIG. 3), the CPU 14 stores the VP memory 1 corresponding to the current block BL.
The 8-bit data VP0 to vP7 at address j of No. 2 is read (step 517 in FIG. 3). Next, the CPU 14
By comparing the vPo-VP7 read from the memory 12 and the 8-bit data held in the internal register for each corresponding bit, a vertical parity check is performed for each bit 0 to 7 in the current block BL (third Figure step 5
18). As is clear, the existence of a bit position where the logical values do not match indicates that a vertical parity error has occurred at the corresponding bit position in the current block BL. Therefore, the CPU 14 performs error correction by inverting the bit data at the bit position where a vertical parity error was detected in step S1g, among the 8-bit memory read data in which a horizontal parity error occurred.
FIG. 3 step 819). In this way, all odd-numbered bit errors in the horizontal direction can be corrected by performing a vertical parity check for each bit position in the corresponding block BL. For example, if the memory data at address 1 of the memory 11 is read and a parity check using its parity bit HP results in an error, then a vertical parity check in block BL to which address 1 belongs results in vertical parity bit VPI, If an error occurs in bits 1 and 2.7 corresponding to VP2゜VP,
Bits 1, 2.7 of memory data at address 1 of memory 11
Error correction can be performed by reversing the .

In the above embodiments, error detection and correction of memory has been described, but the present invention can also be applied to error detection and correction of data stored in external storage media such as disks and magnetic tapes.

[Effect of the Invention J As detailed above, according to the present invention, the parity of the memory read data is normally checked only in the horizontal direction as in the past, and only when a parity error is detected, the parity is checked in the vertical direction of the corresponding block. By performing a parity check in the vertical direction, the result of the vertical parity check indicates which bit of the memory read data is in error, and the parity in the horizontal direction is determined according to the result of the vertical parity check. Error correction can be performed by inverting the relevant bits of memory data that have errors during the check. That is, according to the present invention, error correction can be performed while applying a parity check method with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a data processing device to which the present invention is applied, and FIG. 2 is a flowchart showing the procedure of vertical parity bit update processing in the embodiment.
FIG. 3 is a flowchart showing the procedure of error correction processing in the same embodiment. 11...Memory, 12...VP memory (vertical parity bit memory), 13...PC circuit (parity check circuit), 14...CPU0

Claims (1)

[Claims] A first parity bit is added to each word of data.The memory is divided into multiple blocks in the address direction, and for each block, a second parity bit is added to each data at the same bit position within that block. However, at the time of memory read access, a first parity check is performed using the first parity bit added to the read word data, and if a parity error is detected in this first parity check. perform a second parity check for each bit position of the block in which the corresponding word data exists, using the second parity bit added to each bit position of the block; Of the word data on the memory where a parity error was detected in the first parity check, the bit data at the bit position where a parity error was detected in the second parity check is inverted and corrected. A memory error detection/correction method characterized by: