JPH03168838A - Parity checking system - Google Patents

Abstract

PURPOSE:To eliminate the need for preparing a parity forming part, a parity error detecting part, a parity bit storing circuit, etc., by allowing a CPU to execute parity bit formation and parity bit check. CONSTITUTION:In the case of storing data in an information storage circuit 2 by the CPU 1, the CPU 1 is allowed to form a parity bit corresponding to the data to store the parity bit in the circuit 2 together with the data. At the time of reading out the data from the circuit 2, the read data are checked based upon the parity bit read out together with the data. Consequently, the parity forming part, the parity error detecting part, the parity bit storage circuit, etc., can be omitted, the number of hardwares can be reduced and the whole cost of the system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a parity check method used in information processing systems and the like.

(Prior Art) In various information processing systems, when an error occurs in processed data, it is detected by performing error detection processing such as a parity check to prevent erroneous processing from being performed.

FIG. 3 is a block diagram showing an example of an information processing system having such a parity check function.

The information processing system shown in this figure is a C
A PUIOI, an 8-bit information storage circuit 102 used as a storage area for this CPUIOI, and the CPU
a parity generation unit 103 that generates a parity bit when the IOI writes data to the information storage circuit 102;
A 1-bit parity bit storage circuit 1 that stores the parity bit generated by the parity generation section 103.
04, and a parity error detection unit that reads a parity bit corresponding to the data from the parity bit storage circuit 104 and checks whether the data is correct when the CPUIOI reads data written in the information storage circuit 102. 105, and when a parity error is detected by the parity error detection unit 105, an error processing circuit (not shown) is provided.
Error handling is performed by

(Problem to be Solved by the Invention) However, in the information processing system using the conventional parity check method described above, in order to realize the parity check function, the parity generation section 103, the parity error detection section 105, Verity bit storage circuit 1,
04, the amount of hardware increases accordingly, resulting in a problem that the cost of the entire system increases.

In view of the above circumstances, the present invention makes it possible to eliminate the need for a parity generation section, a parity error detection section, a parity bit storage circuit, etc., thereby reducing the amount of hardware and reducing the cost of the entire system. The purpose is to provide a verity check method.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, a parity check system according to the present invention includes a CPU that performs information processing and an information storage circuit used as a data storage area of this CPU, When the CPU stores data in the information storage circuit, the CPU generates a parity pit corresponding to the data and stores it in the information storage circuit together with the data, and when reading data from the information storage circuit, the CPU generates a parity pit corresponding to the data. It is characterized in that the read data is checked based on the read parity bit.

(Operation) In the above configuration, when data is stored in the information storage circuit by the CPU, a parity pit corresponding to the data is generated by the previous generation CPU and stored in the information storage circuit together with the data, and the information storage circuit When data is read from the , the read data is checked based on the parity pits that are read together with this data.

(Embodiment) FIG. 1 is a block diagram showing an example of an information processing system using an embodiment of the parity check method according to the present invention.

The information processing system shown in this figure is a C
It is equipped with a PUI and an 8-bit information storage circuit 2 used as a storage area of this CPUI, and when the CPUI stores 7-bit data in the information storage circuit 2, 1
A bit parity pit is generated and stored in the information storage circuit 2 together with the data, and when the CPUI reads out 7-bit data from the information storage circuit 2, the parity bit corresponding to this data is also stored together with this data. The data is read out and a parity check is performed, and if there is an error in the read data, error handling is performed.

Next, the operation of this embodiment will be explained with reference to FIGS. 2(a) and 2(b).

First, when the CPUI writes 7-bit data to the information storage circuit 2, the CPU checks this data and sets it to 1.
After generating bit parity pits (step ST1
), this parity bit is added to the data to generate 8-bit data (step ST2), and this is stored in the information storage circuit 2 (step ST3).

Furthermore, when the CPUI reads out 7-bit 1. data from the information storage circuit 2 (step STIO), the CPUI checks the data based on the 1-bit parity pit read together with this data to perform error detection ( Step ST11), if no error is detected, data processing is performed based on the 7-bit data (step ST12), and if an error is detected,
Error processing is performed to prevent incorrect processing caused by errors from being performed (step ST13).

As described above, in this embodiment, since the CPU 1 checks the parity pits and the parity bits, it is possible to eliminate the need for a parity generation section, a parity error detection section, a parity bit storage circuit, etc. This makes it possible to reduce the amount of hardware and reduce the cost of the entire system.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to eliminate the need for a parity generation section, a parity error detection section, a parity bit storage circuit, etc., thereby reducing the amount of hardware and reducing the cost of the entire system. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an information processing system using an embodiment of the parity check method according to the present invention, FIG. 2 is a flowchart showing an example of the operation of the embodiment, and FIG. 1 is a block diagram showing an example of an information processing system using an example of a parity check method. 1...CPU 2...Information storage circuit

Claims (1)

[Claims] (1) A CPU that performs information processing and an information storage circuit used as a data storage area of the CPU, and when the CPU stores data in the information storage circuit, the CPU stores a parity bit corresponding to the data. is generated and stored in the information storage circuit together with the data, and when data is read from the information storage circuit, the read data is checked based on a parity bit read out together with the data. Parity check method.