JPH0667912A - Error detection circuit - Google Patents

Abstract

PURPOSE:To correct two-bit error by means of a simple circuit change in ECC of one-bit error correction and two-bit (or above) error detection. CONSTITUTION:This circuit is provided with an ECC circuit 1 having the generation function of a check bit in write data, a one-bit error correction function in read data, a two-bit error detection function and three or more bits error detection function, ac ECC control circuit 3 controlling the ECC circuit 1 and bit inversion circuit 2 having a function which bit-inverts only specified read data by the instruction of the ECC control circuit 3. When the two-bit error is detected in the read data at the ECC circuit 2, the bit inversion circuit 1 inverts all read data including a checking code one by one bit and the ECC circuit 1 corrects the two-bit error at the time of the one-bit error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of an ECC (Error Check and Correction) circuit for controlling a memory device.

[0002]

2. Description of the Related Art Generally, DRAM (Dynamic Random Acces
The memory control circuit that controls a large-capacity memory device using s Memory) is equipped with an error detection and correction function.
The reason for this is mainly to cope with soft errors (data destruction due to α rays) and minor hard errors that occur accidentally in the semiconductor memory. A normal ECC function in a semiconductor memory is generally a 1-bit error correction and a 2-bit (including 2 bits or more in this case, which will be hereinafter referred to as 2 bits (or more)) error detection.

[0003]

However, the conventional E
The CC circuit has a problem that error correction is impossible when a 2-bit (or more) error occurs. An object of the present invention is to eliminate such drawbacks and to realize an error detection / correction circuit capable of 2-bit error correction by a simple circuit change in ECC for 1-bit error correction and 2-bit (or more) error detection. It is a thing.

[0004]

In order to achieve such an object, according to the present invention, a check bit generating function in write data, a 1-bit error correcting function, a 2-bit error detecting function in read data, and 3 bits or more are provided. The ECC circuit includes an ECC circuit having an error detection function, an ECC control circuit for controlling the ECC circuit, and a bit inverting circuit having a function of inverting only specific read data according to an instruction from the ECC control circuit. When a 2-bit error is detected at 1, the bit inversion circuit inverts all the read data including the check code bit by bit, and when a 1-bit error occurs, the ECC
The circuit is characterized in that a 2-bit error is corrected.

[0005]

A two-bit error correction function is provided by adding a simple circuit to the conventional ECC circuit having a one-bit error correction function and a two-bit (or more) error detection function. When the ECC circuit detects a 2-bit error, the bit inverting circuit inverts the data bit by bit. When a 1-bit error occurs due to this inversion, EC
Correction is performed using the 1-bit error correction function of the C circuit. In this way, a 2-bit error can be corrected.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of an error detection / correction circuit according to the present invention. In the figure, 1 is an ECC circuit, 2 is a bit inversion circuit, and 3 is an ECC control circuit. The ECC circuit 1 has a function of generating check bits in write data, a 1-bit error correction function in read data, a 2-bit error detection function, and a 3-bit or more error function. Then, there are the following two operation modes according to read (Read) and write (Write), and the operation is performed according to an instruction (mode signal: Mode) from the ECC control circuit 3. (1) CB generation mode This is an operation mode for writing to a memory (not shown), and CB calculated by the input data "Data in".
(Check Bit) Outputs the code "Write CB". (2) Error correction detection mode Data "Data in" read from memory and CB code "C"
The syndrome code is calculated from "Bin" and no error (No E
rror) / 1-bit error / 2-bit error / 3-bit or more error status signal is output. If it is a 1-bit error, the data after error correction "Correct Dat
Output a "to the upper level.

The bit inversion circuit 2 inverts the bit designated by the ECC control circuit 3. The ECC control circuit 3 is composed of a shift register 31 and a sequencer 32. The sequencer 32 has a function of receiving a command such as read / write from a host (not shown) and setting a mode in the ECC circuit 1. In the read mode from the memory, if there is no error or 1-bit error according to the status obtained from the ECC circuit 1, the normal end (No
If there is an error of 3 bits or more in the rmal End) status, a data error (Data Error) status is returned as an acknowledge status (Acknowledge Status).
If it is a 2-bit error, no error status (No Error Status) after data correction is performed according to the error processing sequence described later.
s) is returned. The shift register 31 indicates the bit position (inverted) for the bit inversion circuit 2. In this case, the activation from the sequencer 32 causes the operation to be divided into one of the following three operation modes. (1) Clear mode: Clear all data in the shift register (set to "0"). (2) Set mode: The least significant bit (L
Only SB) is set to "1". (3) Shift mode: Data is shifted by 1 bit in the most significant bit (MSB) direction. At this time L
Set "0" to SB. The data width of the shift register is the sum of the data width to the memory and CB (Check Bit). For example, when the ECC circuit 1 has a 32-bit configuration, CB is 7
Since it is a bit, the bit width of the shift register is 39 bits.

The operation in such a configuration will be described below. FIG. 2 is a flowchart showing the operation of the sequencer 32. As can be seen from FIG. 2, the no error, the 1-bit error, and the error of 3 bits or more in the read operation and the write operation are equivalent to the normal ECC control. Here, the operation sequence at the time of 2-bit error, which is a feature of the present invention, will be described. The read data is sequentially inverted bit by bit, one of the bits in which a data error has occurred is detected, and 1-bit error data is generated. Next, the generated 1-bit error data is transferred to the ECC circuit 1
The data is corrected by 1 bit. In the idle state, since the shift register 31 has all data cleared by a Clear command, the bit inverting circuit 2 does not participate in data operation in normal operation. In this way, the 2-bit error can be corrected. It should be noted that if 2-bit errors occur frequently, system performance will be significantly reduced, but the probability of 2-bit (or more) errors is extremely rare, except for the initial failure of hardware. Also, saving the 2-bit error condition is more important than reducing the system performance.

[0009]

As described above, according to the present invention, 1
2-bit error correction is possible by adding a simple circuit to the ECC circuit that has only a bit error correction function.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an error detection / correction circuit according to the present invention.

FIG. 2 is a flowchart showing the operation of a sequencer.

[Explanation of symbols]

 1 ECC circuit 2 bit inversion circuit 3 ECC control circuit 31 shift register 32 sequencer

Claims (1)

[Claims] 1. An ECC circuit having a function of generating a check bit in write data, a 1-bit error correction function in read data, a 2-bit error detection function, and an error detection function of 3 bits or more, and an ECC circuit for controlling this ECC circuit. The ECC circuit includes a control circuit and a bit inverting circuit having a function of inverting bits of only specific read data according to an instruction from the ECC control circuit. When the ECC circuit detects a 2-bit error in read data, the bit inverting circuit An error detection / correction circuit characterized by inverting all read data including a check code bit by bit and correcting a 2-bit error by using the error correction function of the ECC circuit when a 1-bit error occurs. .