JPH0588993A - Memory control system - Google Patents

Abstract

PURPOSE:To reduce probability of generating a 2-bit error by reading out corrected data when an 1-bit error is generated in read data and writing the read data in a memory just after the reading. CONSTITUTION:If an 1-bit error is generated at the time of reading out data from a memory 8, an ECC control circuit 7 corrects the read data, outputs the corrected data to a data bus 2 and sends an 1-bit error generation signal (a) to a rewriting control circuit 5. The circuit 5 sends a retry request signal (b) to a CPU 9 and sends a rewriting cycle signal (c) to a memory access control circuit 3. The circuit 3 sends an ECC control signal (e) to the circuit 7 and sends a memory control signal (h) to the memory 8. The circuit 7 sends the corrected data to the memory 8. Thus rewriting operation in the memory 8 is executed just after reading out data at the time of generating an error.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a memory control system, and more particularly to a control system when an error occurs in read data from a memory.

[0002]

2. Description of the Related Art Conventionally, ECC (Error Checking and Correlation)
In a memory circuit with an ECC having a function of detecting and correcting a 1-bit error and a function of detecting a 2-bit error, if a 1-bit error occurs due to a soft error, the 1-bit error is corrected and then output. It However, even when the CPU detects the occurrence of this 1-bit error, it ignores the 1-bit error without rewriting it and continues execution of the process.
Further, there is also a method in which, when the occurrence of the error is detected, a process of referring to the address register inside the CPU and performing rewriting to the address indicated by the address register is performed later. Furthermore, there is also a system in which an address latch circuit is provided and rewriting is performed to an address latched in the address latch circuit.

In the above-described conventional memory circuit with ECC, when a 1-bit error occurs, if the address at which the 1-bit error occurs is not rewritten, 1 is read every time the address at which the 1-bit error occurs is read. Bit error occurs. As a result, the probability of occurrence of a 2-bit error increases, and the reliability of the memory circuit decreases. On the other hand, when the CPU rewrites, C
There is a drawback that a dedicated program is required for the PU to rewrite. Further, the method of providing the address latch circuit has a drawback that the amount of hardware increases.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to provide a memory control system capable of reducing the probability of occurrence of a 2-bit error.

[0005]

A memory control system according to the present invention includes an error correction means for correcting an error in read data from a predetermined address of a memory, and the corrected data is written to the address immediately after reading the read data. And a writing means.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a memory control system according to the present invention. In the figure,
The memory access control circuit 3 is a circuit that supplies an ECC control signal e corresponding to memory access to the ECC control circuit 7 and a memory control signal h to the memory 8.

The memory refresh circuit 4 is a circuit for sending a memory refresh request signal f to the memory access control circuit 3, and when receiving the memory refresh enable signal g from the memory access control circuit 3, causes the memory 8 to perform a refresh operation. The address of is supplied.

The rewrite control circuit 5 is an ECC control circuit 7
CP according to the 1-bit error occurrence signal a sent from
This is a control circuit that sends a U retry request signal b to the CPU 9 and, at the same time, sends a rewrite cycle signal c to the memory access control circuit 3.

The address selector 6 is a memory input selector for selecting an address supplied from the memory refresh control circuit 4 or the address bus 1 and supplying it to the memory 8.

The ECC control circuit 7 is a circuit which detects a 1-bit error (error) in the read data from the memory 8 and outputs a 1-bit error occurrence signal a. Also, this E
The CC control circuit 7 corrects the data input from the memory 8 according to the ECC control signal e, and sends the corrected data to the memory 8. In addition, 1 is an address bus and 2 is a data bus.

Next, the operation of the present system having such a configuration will be described. When reading data from the memory 8,
When a 1-bit error occurs, the ECC control circuit 7 corrects the data output from the memory 8 and outputs it to the data bus 2. At the same time, the ECC control circuit 7 sends the 1-bit error occurrence signal a to the rewrite control circuit 5. Rewriting control circuit 5 to which the 1-bit error occurrence signal a is input
Sends a retry request signal b to the CPU 9 and at the same time, a rewrite cycle signal c to the memory access control circuit 3.
Is sent.

When the retry request signal b is input, the CPU 9 retries the previous memory read cycle, and the address bus 1
Continue to output the same address on top.

On the other hand, the memory access control circuit 3 to which the rewrite cycle signal c is input does not accept other request signals even if the memory read / write request signal d and the memory refresh request signal f are valid. .. Then, the ECC control signal e for outputting the previously read and corrected data to the memory 8 is sent to the ECC control circuit 7, and the memory control signal h for writing the data to the memory 8 is sent to the memory 8. To do.

The ECC control circuit 7 receives the ECC control signal e and sends the corrected data to the memory 8. Then, the corrected data is written to the corresponding address of the memory 8 according to the memory control signal h and the address on the address bus 1, that is, the same address as the previous read cycle. As described above, when an error occurs, the rewriting operation to the memory 8 is performed immediately after the reading.

After the rewriting operation, the rewriting cycle signal c becomes invalid, and the memory access control circuit 3 causes the CPU 9 to operate.
In response to the memory read request by the retry, a normal memory read cycle is performed, and the CPU 9 ends the retry.

However, even when the CPU 9 retries,
When a bit error occurs, it is obviously regarded as a fixed failure of the memory 8 and there is no need to rewrite.

As described above, according to the memory control system of this embodiment, when the ECC control circuit outputs the error detection signal, the rewrite control circuit outputs the CPU retry request signal and the rewrite cycle signal. , The corrected data can be rewritten by writing the previously read and corrected data to the same address as the address in the previous read cycle output by the retry of the CPU.

[0019]

As described above, according to the present invention, 1
When a bit error occurs, rewriting is always performed after correction, so that unlike the conventional method, there is an effect that the probability of a 2-bit error occurring can be reduced.
Further, since this rewriting operation is performed by utilizing the retry of the CPU, there is no need for a dedicated program for rewriting, and the processing efficiency of the CPU can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control system according to an embodiment of the present invention.

[Explanation of symbols]

 1 Address Bus 2 Data Bus 3 Memory Access Control Circuit 4 Memory Refresh Control Circuit 5 Rewrite Control Circuit 6 Address Selector 7 ECC Control Circuit 8 Memory 9 CPU

Claims (1)

[Claims] 1. An error correction means for correcting an error in read data from a predetermined address of a memory, and a write means for writing the corrected data to the address immediately after reading the read data. And memory control system.