JP2586072B2 - Storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to the control of a storage device that performs an interlaced operation, and more particularly, to the control when a write data parity error is detected.

(Prior Art) Conventionally, when a write operation of M interlaces (M: positive integer> 1) is executed in units of N bytes (N: positive integer> 1), any one of the first to Mth N-byte When a write data parity error is detected in the write data, an error reply is returned to the system controller, causing a system down.

(Problem to be Solved by the Invention) A method of returning an error reply to the system control device when a parity error is detected in any of the N-byte write data of Nos. 1 to M during the above-described conventional write. In the M-interlacing operation at the time of reading, N bytes in which a write data parity error has occurred can be read. However, if the N bytes are unnecessary for the system controller, or if the address is changed, If rewriting is performed before reading, there is a disadvantage that a system down occurs.

It is an object of the present invention to perform all writing / writing from the system controller.
In response to a read instruction or a partial write instruction, all write / read operations of the M interlace are performed in units of N bytes,
Alternatively, when a partial write operation is performed and an error reply is returned when an error is detected, a write data parity error is detected in a time series of N bytes at the time of writing, and the detection signal is time-series along with the N byte data in a memory matrix circuit. The N-byte valid bit signal sent from the system controller in N-byte units in time series at the time of writing and reading is set in M registers in time series, and the N-byte units read in time series from the memory matrix circuit Is set in the other M registers, and the logical sum of the output signals of these registers is calculated, and the logical sum of the M logical product signals is sent to the system controller as an error reply signal. And to provide a storage device configured to reduce the possibility of system down. .

(Means for Solving the Problems) A storage device according to the present invention is capable of performing all write / read operations or partial operations of M interlaces in N bytes in response to a full write / read or partial write instruction from a system controller. When a write operation is executed and an error is detected, an error reply is returned. The parity check circuit, the memory matrix circuit, the M first registers, the M second registers, and the error reply And a control circuit.

The parity check circuit is for detecting a write data parity error in a time series of N bytes at the time of writing and transmitting a detection signal.

The memory matrix circuit is for writing detection signals in N series together with N bytes of data.

The M first registers are for setting, in time series, N-byte effective bit signals sent from the system control unit in time series in units of N bytes when reading the contents of the memory matrix circuit. .

The M second registers are for setting detection signals in N-byte units read out in time series from the memory matrix circuit.

The error reply control circuit calculates the logical product of the output signals of the first and second registers, and sends the logical sum of the M logical product signals to the system control device as an error reply signal.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. In FIG. 1, 1 is a main control circuit, 2
Is an error reply control circuit, 3 is a memory matrix circuit, 4, 7, 11, and 16 are registers, 5 is a check bit generation circuit, 6 is a parity check circuit, 8 is a syndrome generation circuit, 9 is a decoder, and 10 is a correction circuit. It is.

Signal line from system control circuit (not shown)
When a request is transferred via the line 20 and a command and a byte instruction are transferred via the signal line 21, the storage device receives these signals. In the main control circuit 1, signal lines
The command on 21 is decoded to start execution of the write operation. To start the execution, an in-device control signal is generated on a signal line 23. The write data on the signal line 25 is set in the register 4 and sent to the memory matrix circuit 3.

Next, the address (not shown) and RAS / CA
At the timing of S / WE (signal line 22), data is written to the designated address of the memory matrix circuit 3 via the signal line 26, and parity is written to another designated address of the memory matrix circuit 3 via the signal line 27. Check bits are written. Signal line
The write data on 26 is parity-checked by the parity check circuit 6, and the detection signal on the signal line 28 is written to the memory matrix circuit 3 in the same manner as the data (signal line 26) and the check bit (signal line 27).

In the subsequent operations, as in the first operation, the data on the signal line 26, the check bits on the signal line 27, and the detection signal on the signal line 28 are written in a time series in units of 4 bytes, and a 16-byte write operation is performed. Is completed. At this time, even if a write data parity error is detected, writing is performed without returning an error reply.

Next, when a request is transferred from the system control device via the signal line 20 and a command is transferred via the signal line 21, the storage device receives these signals and the main control circuit 1 controls the signal line. The command on 21 is decoded to start execution of the read operation. At the start of execution, signal line 23
Above, an in-device control signal is generated. Next, the data / check bit at the designated address is read out on the signal line 31 by the address and the RAS / CAS timing on the signal line 22 and the write data parity error detection signal is read out on the signal line 29. Is done.

The data on the signal line 31 is sent to the system controller via the syndrome generation circuit 8, the decoder, the correction circuit 10, and the register 11. The detection signal on the signal line 29 is sent to the error reply control circuit 2 via the register 7. Subsequent operations are performed one after another for each unit clock in units of 4 bytes, as in the first operation.

At any time, the 4-byte valid bit signal on the signal line 17 indicating whether the 4-byte data to be read first at the same timing as the request on the signal line 20 is required by the system control unit is controlled by the system control unit. Sent from the device. Similarly, a 4-byte valid bit signal on the signal line 17 corresponding to the second to fourth 4-byte read data is successively transmitted for each clock.

The valid bit signal transmitted on the signal line 17 is transmitted to the error reply control device 2 via the register 16.
In the error reply control circuit 2, the logical product of the effective bit signal on the signal line 18 and the error detection signal on the signal line 30 is obtained in a time series, and when the logical product becomes a logical value "1", the signal is obtained. An error reply is sent back to the system controller via line 19.

FIG. 2 shows the first and third storage devices in the storage device of FIG.
FIG. 9 is a timing chart of signal waveforms showing a case where a byte is valid and the second and fourth bytes are invalid. The write data parity error detected at the time of writing is registered second, but no error reply is returned because the second four bytes are not required by the system controller.

FIG. 3 shows the first and fourth data storage devices in the storage device shown in FIG.
FIG. 9 is a timing chart of signals indicating a case where a byte is valid and a second and a third are invalid. Since the fourth error required by the system controller is registered, an error reply is returned.

(Effects of the Invention) As described above, the present invention provides a method of performing (N bytes) × (M interlace) full write / read or partial write operation, which is performed when a write data parity detected in N bytes at the time of writing is used. Without reporting the detection error signal to the system controller as an error, the memory matrix circuit stores the M data in N-byte units in time series with the write data.
Only when a write data parity error detection signal of valid N-byte data is read after receiving a valid bit signal indicating whether the first to M-th N-byte data is valid at the time of writing and reading Then, by returning an error reply signal to the system controller and controlling not to return the error reply signal when the data is invalid N bytes, there is an effect that the reliability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a storage device according to the present invention. FIGS. 2 and 3 are timing diagrams showing signal waveforms of the storage device of FIG. DESCRIPTION OF SYMBOLS 1 ... Main control circuit 2 ... Error reply control circuit 3 ... Memory matrix circuit 4,7,11,16 ... Register 5 ... Check bit generation circuit 6 ... Parity check circuit 8 ... Syndrome generation circuit 9 ... ... Decoder, 10 ... Correction circuit 17-35 ... Signal line

Claims (1)

(57) [Claims] 1. An M-interlace full-write / read-out operation or a partial-write operation in units of N bytes in response to a full-write / read-out or a partial-write instruction from a system controller, and an error reply is sent when an error is detected. A parity check circuit for detecting a write data parity error in units of N bytes (N: positive integer> 1) in time series at the time of writing and sending out a detection signal, A memory matrix circuit for writing signals in N series together with N bytes of data, and an N-byte effective bit signal sent from the system controller in time series in units of N bytes when reading the contents of the memory matrix circuit (M: positive integer> 1) of first registers for setting time series in ANDing the output signals of the first and second registers with M second registers for setting the detection signal in N-byte units read out at the same time, and obtaining the M logical product signals And an error reply control circuit for sending a logical sum of the two to the system control device as an error reply signal.