JP2818659B2 - Error correction method - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problem Actions Embodiment I. Correspondence between embodiment and FIG. 1 II Configuration of the embodiment (i) During normal operation (ii) When a 2-bit error occurs (iii) When a first 1-bit error occurs (iv) When re-executing IV. Summary of the embodiment V. Modifications of the invention Effect [Outline] The purpose of this error correction method is to read out data containing an error correction code and determine the location of the error when an error occurs. Then, the data including the error correction code stored in the memory is read out from the memory and stored in the data holding means. If the error detection means detects that there is an error in the data,
The data in which the error has been detected is corrected by the correction unit, and stored again in the data holding unit. The error detection means detects whether or not the correction data stored in the data holding means has an error, and the determination means determines the location of the error according to the error detection result.

[Industrial applications]

The present invention relates to an error correction method, and more particularly to an error correction method in which data including an error correction code is read and an error occurrence position is determined when an error occurs.

[Conventional technology]

In recent years, with the development of semiconductor technology, the degree of integration of logic elements used in computers has been improved, and the operation cycle time has been shortened. In addition, with the improvement of the function of the logic element, problems such as deterioration of the part retention of the element and an increase in the defect rate of the element are caused.

To cope with such a problem, there is a method of adding an error correction code (hereinafter, referred to as ECC) to data.
For example, an error correction code (hereinafter, referred to as ECC) is added to data stored in a memory or the like, an error is verified when the data is read, and data is corrected when an error occurs.

FIG. 4 shows a configuration of a conventional example for correcting read data.

In the figure, a correction circuit for correcting data read from the memory 411 includes a write data latch 463 for temporarily holding data to be supplied to the memory 411, and a read data latch 42 for temporarily holding data read from the memory 411.
1, an address latch 453 for temporarily storing address data to be supplied to the memory 411, an error address latch 455, an error detection unit 431 for comparing the ECC part of data with other parts, and performing error detection, and an error detection unit 431. An error correction control unit 441 that performs control according to the detection result of the unit 431, an error correction unit 443 that corrects data, and two selectors 451 and 461 are provided.

When storing data in the memory 411, first, the selector 4
The data including the ECC is stored in the write data latch 463 via 61. Also, address latch 4 via selector 451
The address data is stored in 53.

Next, the address data stored in the address latch 453 and the data stored in the write data latch 463 are supplied to the memory 411, and the memory 411 is supplied from the write data latch 463 to a storage location specified by the address data. Store the data.

FIG. 5 shows an operation procedure when error correction is performed on read data.

First, data is read and stored in the read data latch 421 (step 511). Address data is supplied from the address latch 453 to the memory 411, and the corresponding data is read out and stored in the read data latch 421 in the same manner as the operation of storing data in the memory 411.

Next, the error detection unit 431 compares the read data (data other than the ECC) stored in the read data
And performs error detection, and sends the detection result to the error correction control unit 441 (step 512).

The error correction control unit 441 determines whether there is an error in the read data according to the detection result (step 51).
3). If a negative determination is made (when there is no error), the process returns to step 511 and repeats the processing.

If a positive determination is made in step 513 (if there is an error), the error correction control unit 441 sends an error signal to the error correction unit 443. Upon receiving the error signal, the error correction unit 443
Corrects the read data according to the read data and ECC stored in the read data latch 421 (step 514).

Next, the data (read data and ECC) corrected by the error correction unit 443 is written to the memory 411 (step
515). The address data corresponding to the data in which the error has occurred is held in the error address latch 455, and the address data is stored in the address latch 453 via the selector 451. The corrected data output from the error correction unit 443 is stored in the write data latch 463 via the selector 461. Thereafter, the corrected data stored in the write data latch 463 is stored in the storage location specified by the address data stored in the address latch 453.

[Problems to be solved by the invention]

By the way, in the conventional method described above, the memory 411
Other logic elements (read data latch 421, error detector
431), a memory error (a hardware failure of the memory 411 or a software failure of stored data) is erroneously detected when an error occurs.

For example, even if the data read from the memory 411 is normal, when an error is erroneously detected by the error detection unit 431, the data is corrected by the error correction unit 443, and the corrected data (erroneous data) is stored in the memory 411. Will be stored again. In particular, recently, as the degree of integration of logic elements has increased, the frequency of occurrence of failures in logic elements other than the memory 411 has also increased, and it is necessary to correct data errors and deal with failures of elements other than the memory 411. There is a need for an error correction method that can be implemented.

The present invention has been made in view of such a point, and an object of the present invention is to provide an error correction method capable of distinguishing between a memory error and an error of another element.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the present invention.

In this figure, a memory 111 stores data including an error correction code.

The data holding means 121 stores the data read from the memory 111.

The error detecting means 131 performs an error detection on the data stored in the data holding means 121.

The correction means 141 corrects the data stored in the data holding means 121 and causes the data holding means 121 to store the corrected data.

The determining means 151 determines an error occurrence location based on the detection result by the error detecting means 131.

When the error detecting means 131 of the error correction system configured as described above detects an error in the data stored in the data holding means 121, the data corrected by the correcting means 141 is stored in the data holding means 121. Performing error detection of the corrected data by the error detection means 131,
By giving the detection result to the determination means 151,
The invention according to claim 1 is configured.

(Operation)

Data including an error correction code is stored in the memory 111.
The data is read from the memory 111 and the data holding means 1
The data stored in the data storage unit 121 and the data stored in the data storage unit 121 are checked by the error detection unit 131 for errors.

When the error detecting unit 131 detects an error, the correcting unit 141 corrects the data stored in the data holding unit 121 and causes the data holding unit 121 to hold the data again.

The error detecting means 131 detects whether or not the corrected data stored in the data holding means 121 has an error.

The error detection result is given to the determination means 151 to determine the location where the error has occurred.

Therefore, it is possible to know whether the error has occurred in the memory or in an element other than the memory.

〔Example〕

Hereinafter, an embodiment of the invention described in claim 1 will be described in detail with reference to the drawings.

FIG. 2 shows a configuration of an embodiment to which the error correction system according to the first aspect of the present invention is applied.

I. Correspondence Between Embodiment and FIG. 1 Here, the correspondence between the embodiment of the invention described in claim 1 and FIG. 1 will be described.

The memory 111 corresponds to a control storage (hereinafter, referred to as CS) 211.

The data holding unit 121 corresponds to the read data latch 223.

The error detection unit 131 corresponds to the error detection unit 231 and the error correction control unit 251.

 The correction unit 141 corresponds to the error correction unit 241.

The determination unit 151 includes an error correction control unit 251, a re-execution flag 2
Equivalent to 53.

Assuming that the above-mentioned correspondence exists, an embodiment of the present invention will be described below.

II. Configuration of Embodiment In FIG. 2, a system (for example, a computer system) to which the error correction method according to claim 1 is applied is
CS211 to store microprogram and corresponding ECC
An error detection unit 231 that detects an error by comparing the read microprogram with the ECC, an error correction control unit 251 that performs control associated with error detection, and corrects data (microprogram) when an error occurs. An error correction unit 241, a re-execution flag 253 storing a flag according to the presence or absence of an error, a write data latch 263 holding a microprogram and an ECC stored in the CS 211,
A read data latch 223 for holding a microprogram and ECC read from the CS 211, an address latch 273 for holding address data to be supplied to the CS 211, and an error address latch 27 for holding address data when an error occurs.
5 and 3 selectors that select and output one of the two inputs 2
21,261,271.

Address data for specifying the address of CS 211 is introduced to the first input terminal of selector 271. selector
The output terminal of the address latch 273 is connected to the input terminal of the address latch 273, and the output terminal of the address latch 273 is connected to the address terminal of the CS 211 and the input terminal of the error address latch 275. The output terminal of the error address latch 275 is the selector 271
Is connected to the second input terminal of.

The first input terminal of the selector 261 has write data (micro program and corresponding EC) stored in CS 211.
C) is introduced. The output terminal of the selector 261 is connected to the input terminal of the write data latch 263, and the output terminal of the write data latch 263 is connected to the data terminal (input side) of the CS 211.

Data (microprogram, ECC) output from the data terminal (output side) of the CS 211 is supplied to a first input terminal of the selector 221. The output terminal of the selector 221 is connected to the input terminal of the read data latch 223, and the output terminal of the read data latch 223 is connected to the input terminal of the error detection unit 231 and the error correction unit 241.

The error detection unit 231 detects an error based on the data supplied from the read data latch 223. The detection result is supplied to the error correction control unit 251.

The error correction control unit 251 is connected to the re-execution flag 253 and the error correction unit 241, and sets and resets the re-execution flag 253 according to the detection result from the error detection unit 231. Send instructions to

Note that each latch and each selector operate in response to an instruction signal sent from the error correction control unit 251, and a connection line with the error correction control unit 251 in the figure is omitted.

When writing write data (microprogram, ECC) to CS211, first, the write data latch 263
The write data introduced via the selector 261 is held, and they are supplied to the data terminal (input side) of the CS 211.

Further, the address latch 273 holds the address data introduced via the selector 271, and the address data is supplied to the address terminal of the CS 211.

The CS 211 stores the write data supplied to the data terminal in a storage location specified by the address data supplied to the address terminal.

When reading the microprogram stored in the CS 211, the address latch 273 first holds the address data introduced via the selector 271 and the address data is supplied to the address terminal of the CS 211.

CS211 is a microprogram and ECC stored in the location specified by the supplied address data.
Is output. Those data are held in the read data latch 223 via the selector 221. The microprogram held in the read data latch 223 is loaded into a processing device or the like (not shown) and executed.

III. Operation of Embodiment Next, the operation of the embodiment of the first aspect of the present invention will be described.

Now, as ECC corresponding to microprogram,
It is assumed that a code for 1-bit error correction and 2-bit error detection is considered, and the error detected in the embodiment is either a 1-bit error or a 2-bit error.

 FIG. 3 shows an operation procedure in the embodiment.

(I) During normal operation First, a microprogram and ECC are read from CS 211 (step 311). These read data are held in the read data latch 223.

Next, the error detection unit 231 detects an error in the read data (step 312). As the detection result, information such as the presence or absence of error detection, whether a 1-bit error or a 2-bit error is sent to the error correction control unit 251.

Next, the error correction control unit 251 determines whether or not the process is a re-execution process (step 313). At the time of the first error detection processing for the data read from the CS 211 (when the re-execution flag 253 is reset), a negative determination is made and it is determined whether or not an error has occurred (step 314). If no error is detected, a negative determination is made.

Thereafter, the process returns to step 311 to repeat the processing. An instruction is sent from the error correction control unit 251 to the address latch 273, and the next microprogram is read.

(Ii) When a 2-bit error occurs: A positive determination is made in step 314 (when an error occurs)
Then, the error correction control unit 251 determines whether the generated error is a two-bit error (step 315). If a two-bit error has occurred, a positive determination is made.

Next, the error correction control unit 251 stops the reading process of the microprogram (step 316), notifies the occurrence of a failure (step 317), and ends the process. For example, an error signal for indicating occurrence of a 2-bit error is sent to an external processing device, or a 2-bit error warning lamp is turned on.

(Iii) At the time of the first occurrence of a 1-bit error If a negative determination is made in the determination at step 315 (if not a 2-bit error, that is, a 1-bit error), then the error correction control unit 251 sets the re-execution flag 253 The data "1" is stored) (step 318).

Further, error correction control section 251 sends a correction instruction to error correction section 241 and error correction section 241 corrects the microprogram according to the instruction (step 319). The error correction unit 241 reads the microprogram and the ECC held in the read data latch 223, and corrects an error bit in the microprogram.

Next, the corrected microprogram and the corresponding ECC are stored in CS 211 (step 320), and selector 271 is stored.
And the address data at the time of occurrence of an error held in the error address latch 275 is held in the address latch 273. The address data held in the address latch 273 is supplied to the address terminal of the CS 211. Further, the selector 261 is switched to hold the corrected microprogram and ECC in the write data latch 263. Those data held in the write data latch 263 are supplied to the data terminal of CS211.

Further, the selector 221 is switched to hold the corrected microprogram and ECC in the read data latch 223 (step 321).

Thereafter, the process returns to step 312 (error detection) to repeat the processing.

(Iv) At the time of re-execution If the determination in step 313 is affirmative (when the re-execution flag 253 is set in step 318), then the error correction control unit 251 stops the reading process of the micro program (step 322). At the same time, it is determined whether an error has occurred (step 323).

If a negative determination is made, the error correction control unit 251 outputs an error signal indicating that a failure has occurred in the CS 211 (step
324), end the process.

If an affirmative determination is made in step 323, an error signal indicating that a failure has occurred in any of the selector 221, the read data latch 223, the error detector 231 and the error corrector 241 other than the CS 211 is output (step 325). , And the process ends.

IV. Summary of Examples As described above, the microprogram and the corresponding E
CC and the data read from CS 211 are stored in read data latch 223. The error detection unit 231 detects an error in the data, and when there is no error in the data, continues reading the data from the CS 211.

If there is a 1-bit error in the data read from CS 211 (data supplied from CS 211 to read data latch 223), error correction section 241 corrects the data, writes the corrected data to CS 211, and reads the read data. It is held by the latch 223.

Next, error detection is performed on the correction data held in the read data latch 223, and if no error has occurred again, it is determined that there is a failure in CS211.If an error has occurred again, CS211 has been detected. It is determined that there is a failure in the other logic elements.

If the error detection unit 231 detects a 2-bit error, it is impossible to correct the data and it is impossible to determine the above-mentioned faulty part. Therefore, the 2-bit error is notified to the outside and the processing is terminated. .

Therefore, when an error occurs in the data read from the CS 211, the data is corrected, and the error detection is performed again on the corrected data, thereby determining the location of the error occurrence (CS211 or other logic). Erroneous detection of a memory error can be prevented.

V. Modifications of the Invention In the embodiment of the invention described in claim 1, control storage for storing a microprogram is considered as CS 211, but other memories (ROM, RAM, etc.) are also claimed. The invention described in Item 1 can be applied. When a read-only element such as a ROM is considered as the memory, the process of step 320 (rewriting of the memory) in FIG. 3 is omitted.

Further, as the ECC of the embodiment, 1-bit error correction, 2
Although a method of detecting a bit error is considered, any method can be used as long as the corresponding data can be corrected.

Further, in "I. Correspondence between the embodiment and FIG. 1",
Although the correspondence between the invention described in claim 1 and the embodiment has been described, the present invention is not limited to this, and those skilled in the art can easily presume that the present invention has various modifications. Will.

〔The invention's effect〕

As described above, according to the present invention, when an error occurs in data, the data is corrected by the correction means, stored in the data holding means, and the error occurrence location is determined based on the result of the error detection performed again. Therefore, it is possible to determine whether an error has occurred in the memory or an element other than the memory.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 1, FIG. 2 is a configuration diagram of an embodiment to which the error correction method of the invention is applied, FIG. FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an operation explanatory diagram of the conventional example. In the figure, 111 is a memory, 121 is data holding means, 131 is error detecting means, 141 is correcting means, 151 is discriminating means, 211 is CS, 221, 261 and 271 are selectors, 223 is a read data latch, 231 is an error detecting section, 241 Is an error correction unit, 251 is an error correction control unit, 253 is a re-execution flag, 263 is a lard data latch, 273 is an address latch, and 275 is an error address latch.

Claims (1)

(57) [Claims] A memory for storing data including an error correction code; a data holding means for storing data read from the memory; an error detection means for detecting an error in data stored in the data holding means; Correcting means for correcting data stored in the data holding means and storing the corrected data in the data holding means; and determining means for determining an error occurrence location based on a detection result by the error detecting means. When the error detecting means detects an error in the data stored in the data holding means, the data corrected by the correcting means is stored in the data holding means, and the error detection of the corrected data is performed by the error detection. And an error correction method, wherein the detection result is provided to the determination means.