JP2000099410A - Memory control circuit and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an error correctable memory control circuit capable of rewriting read data including the bits of an error detecting/correcting code(ECC) in a memory as it is when an uncorrectable error is generated in the ECC at the time of reading out data from the memory by partial writing. SOLUTION: Data read out from a data memory DATA and an ECC memory ECC are respectively temporarily stored in a read buffer RDB and a buffer ECB. The data stored in the RDB and the ECB are checked by an ECC checking part ECH, and when an error is detected, error information is generated from the ECH and a selector control part SEL switches respective selectors EDS, EES to the RDB side and the ECB side. Then data are written in the DATA and the ECC. Althrough the ECH is not included in a data route, respective data are inputted to the ECH to check the existence of an error, and when an error exists, the ECC detects/corrects the error and stores errorless data in respective memories DATA, ECC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection / correction code (ECC: Erro) for an information processing apparatus for performing posted write and a main memory such as a dynamic random memory.
r Checking and Correcting) function and a data processing device.

[0002]

2. Description of the Related Art An error in data stored in a main storage device caused by a hardware cause such as a storage device failure causes a major failure in the entire computer system. Therefore, by adding an error correction code to the main storage device,
Corrects errors in the original information. For example, the number of bits k for 1-bit error correction is the number of bits n of the original information.
It doesn't increase so much even if it gets bigger. If n = 16, k
= 5. Many of the errors in the storage element have a simultaneous error bit number of 1, and a simultaneous error of 2 bits or more is rare.
The error correction circuit in this case includes a storage device, an error detection circuit that receives a correction bit and a data bit from the storage device and outputs an error bit inversion code, and an error detection circuit that outputs the error bit inversion code and the preceding data bit. And a bit inversion circuit for inputting and outputting corrected data. The corrected data is sent to the CPU via the data bus. In recent years, an error correction circuit is often built in an LSI chip.

FIG. 4 shows an example of a memory control circuit having a data error correction circuit for correcting data of 2 bits or more.
This will be described with reference to FIG. In FIG. 4, BUS is a system bus, WDB is a write buffer, WDS is a write data selector (to select BUS data X and ECC check data) circuit, ECG is an ECC bit generator, DATA is memory data, and ECH is ECC check circuit, RDB is read data buffer for data part,
ECB is read data buffer for ECC bit, ECC
Is a memory ECC bit memory.

In this memory control circuit, memory data is fetched from a system bus BUS and a temporary buffer WDB
, And the memory data is selected by the WDS by the write data and stored in one DATA of the memory, and the ECC bit is generated by the ECG according to the memory data and stored in one ECC of the other memory.

In this case, a memory write buffer (MW
In a conventional memory control circuit of an information processing apparatus that performs posted write with B), in a partial write in which a part of memory data is rewritten, DATA and E of the memory are used.
FIG. 5 shows a data flow path for error correction in the memory in the partial write at the time of reading from the CC. Each data read from DATA and ECC is transmitted through each buffer RDB and ECB to the ECH. Performs ECC check, corrects the error and selects with the selector WDS.
Update data was written to DATA and ECC of the memory, respectively. However, when an uncorrectable ECC error (when two or more bits are invalid) occurs, the DAT
A and ECC are not written, and then a memory read for that address occurs and it is determined that an ECC error has occurred, thereby notifying an error warning.

Here, posted write means that when a memory write by the bus master of the BUS occurs, data is held in the write buffer WDB, the memory write cycle on the BUS side ends, and then the memory write cycle on the memory side occurs. Means that the data of the WDB is written to the memory. In the case of partial writing, in the case of writing in byte units (for example, 8 bits), since the ECC is generated in word units (for example, 16 bits), partial writing is performed when the byte units and word units are different.

[0007]

However, in such a memory control circuit, since there is no address of data that has not been written, even if an error is notified, the place where the error occurs is the memory control circuit itself. In some cases, for example, when an ECC error occurs due to a failure of a memory control circuit or external noise, even if the content of the data in the memory is correct, even if the error is read from the address where the error occurred due to an external factor, an error occurs. Does not occur, and as a result, there is a possibility that a catastrophic failure such as garbled data due to write omission at the time of partial write in which an ECC error has occurred may occur.

An object of the present invention is to provide a memory control circuit that can correct an error even if an ECC error occurs in a memory control circuit having an ECC itself.

[0009]

According to the present invention, there is provided an information processing apparatus having a memory control circuit connected to a system bus for performing a posted write by a memory write buffer, wherein the memory control circuit is configured to perform a partial write from a memory in a partial write. At the time of reading, the error detection / correction code (EC
When an uncorrectable error (C: Error Checking and Correcting) occurs, the read data including the bit of the error detection / correction code is written back to the memory as it is.

The information processing apparatus according to the present invention further comprises a write buffer for temporarily storing write data from the system bus, a write data selector for selecting one of the write data and error-corrected data,
An error data selector for selecting one of the output of the write data selector and the read data, and a data portion of a memory for storing an output of the error data selector.
An error correction generation unit that generates an error correction bit based on the output data of the write data selector, an error correction selector that selects one of the error correction bit and the read correction bit, and an output of the error correction selector. An error detection and correction unit of a memory to be checked, an error detection and correction unit for checking data errors based on outputs of the data unit and the error detection and correction unit of the memory, and correcting the error;
A selector control unit that controls the error data selector and the error correction selector based on the presence or absence of an error in the error detection and correction unit.

According to another aspect of the present invention, there is provided a memory control circuit for detecting and correcting a data error, comprising: a write buffer for temporarily storing write data from a system bus; A write data selector, an error data selector for selecting one of the output of the write data selector and the read data, a data portion of a memory for storing an output of the error data selector, and an output of the write data selector. An error correction generation unit that generates an error correction bit based on data, an error correction selector that selects one of the error correction bit and the read correction bit,
An error detection and correction unit of a memory that stores an output of the error correction selector, a read data buffer that temporarily stores data read from a data unit of the memory,
A read error correction buffer for temporarily storing data read from the error detection and correction unit of the memory, and an error for checking and correcting data errors based on outputs from the read data buffer and the read error correction buffer. A detection / correction unit; and a selector control unit that controls the error data selector and the error correction selector based on the presence or absence of an error in the error detection / correction unit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, WDB is a data buffer for temporarily storing write data from the system bus BUS, RDB is a buffer for temporarily storing data from DATA in the memory, and ECB is an EC in the memory of the memory.
This buffer temporarily holds the ECC bit from C.
WDS selects data from WDB and ECH and EDS
Selects data from RDB and WDS, EES selects EC
A selector for selecting and switching data from G and ECB. ECG and ECH are an ECC generator and a checker, respectively. SEL is a circuit that controls EDS and EES based on error information from ECH. DA
TA and ECC are memories MEM, and as data and ECC bits, for example, 32-bit data DA
TA and 16 ECC bits of the 32-bit data error correction code are stored and read as a pair. Further, in FIG. 1, the signal lines with diagonal lines of the respective signal lines indicate a bus configuration.

Further, the information processing apparatus for detecting and correcting a data error according to the present embodiment and a memory control circuit used for the information processing apparatus will be specifically described. A write buffer WDB for temporarily storing write data from a system bus is provided. ,
A write data selector WDS for selecting one of the write data and the error-corrected data; an error data selector EDS for selecting one of the output of the write data selector and the read data; and an output of the error data selector. Data part DAT of the memory for storing
A, an error correction generation unit ECG that generates error correction bits based on output data of the write data selector,
An error correction selector EES for selecting one of the error correction bit and the read correction bit; and an error detection and correction unit E of a memory for storing an output of the error correction selector.
CC, a read data buffer RDS for temporarily storing data read from the data section of the memory, a read error correction buffer ECB for temporarily storing data read from the error detection and correction section of the memory,
Check the data error based on the output of the read data buffer and the read error correction buffer,
An error detection and correction unit ECH for correcting errors, and a selector control unit SE for controlling the error data selector and the error correction selector based on the presence or absence of an error in the error detection and correction unit.
L. The memory control circuit may include other components, for example, the selector ED
A memory buffer may be inserted between S, EES and DATA, ECC of the memory for stable procedures and data processing.

[Operation of this Embodiment] The operation of this embodiment will be described below. Referring to FIG. 1, when a memory write by the BUS bus master occurs, the data is held in the WDB, and the memory write cycle on the BUS side ends. Then, by the memory write cycle on the memory side,
WDB data is written to the memory (this is called posted write). EC for write in byte unit
Since C is generated in word units, it is a partial write (partial write). In the partial write, data is read once in word units from DATA in the memory, a data error is checked by the ECH via the read buffer RDB, error correction (correction) is performed, and a corresponding byte in the data is written in the WDB by the WDS. Replace with data, EC
G generates ECC data, and DATA,
This is completed by the operation of writing to the ECC.

FIG. 2 shows a data read / write path in partial write. Each data read from DATA and ECC of the memory is stored in buffer RDB and EC
B, temporarily read the data by ECH, check for data errors, and perform error data correction.
An error data correction signal is selected by DS, and is written to DATA via EDS at a previous address as update data. The error data correction signal generates ECC bits based on the error data correction signal in EDG, and is stored in the ECC via EES.

Next, it is assumed that an uncorrectable error of the ECC has occurred during reading from DATA in the memory.
FIG. 3 shows a data flow path when an uncorrectable error of the ECC occurs. Data read from DATA and ECC are temporarily stored in RDB and ECB, respectively. The data of the RDB and ECB are checked by the ECH, and when the error is detected, error information is generated from the ECH.
The ES is switched between the RDB side and the ECB side. And DA
Writing to TA and ECC is performed. In this case, E
Although the CH does not enter the data path, each data is input and an error check is performed.
If there is no error, the RDB and ECB sides are selected in EDS and EES.
And ECC. If there is an error, error detection / correction is performed by the ECC, the data is corrected to error-free data, input to the write data selector WDS, and the data memory DATA and the EC corresponding to the corrected data are input.
The C data is stored in the ECC memory.

[0018]

According to the present invention, when reading from a memory in a partial write, an uncorrectable error of the ECC occurs due to a failure of the memory control circuit or external noise even though the contents of the memory are correct. Even in this case, the read data, including the ECC bit, is written back to the memory as it is, that is, by rewriting the data that was normal data to incorrect data, it is ensured that the memory read for the address where the error occurred causes the EC to be read.
By generating the C error, the reliability of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a memory control circuit according to the present invention.

FIG. 2 is a data path diagram in a normal state of a memory control circuit according to the present invention.

FIG. 3 is a data path diagram of a memory control circuit according to the present invention in an irregular state.

FIG. 4 is a configuration block diagram of a conventional memory control circuit.

FIG. 5 is a data path diagram of a conventional memory control circuit.

[Explanation of symbols]

BUS System bus WDB Write data buffer WDS Write data buffer ECG ECC bit generator EES Write data selection circuit (ECC check data and memory read data data section) EES write data selection circuit (ECC generator data and memory read data ECC section) DATA Memory data Section ECC memory ECC data section RDB read data buffer (data section) ECB read data buffer (ECC bit section) ECH ECC check circuit SEL selector control circuit

Claims (5)

[Claims] 1. An information processing apparatus comprising a memory control circuit connected to a system bus for performing posted write by a memory write buffer, wherein the memory control circuit detects / corrects an error when reading from a memory in a partial write. Code (ECC: Error Checking and
Correcting) uncorrectable error,
An information processing apparatus, wherein data read out, including bits of the error detection / correction code, is written back to the memory as it is. 2. The information processing apparatus according to claim 1, wherein the uncorrectable error of the error detection / correction code is error-free normal data. 3. A write buffer for temporarily storing write data from a system bus, a write data selector for selecting one of the write data and error-corrected data, and an output and read of the write data selector. An error data selector for selecting any of data, a data portion of a memory for storing an output of the error data selector, and an error correction generation portion for generating an error correction bit based on output data of the write data selector, An error correction selector for selecting any one of the error correction bit and the read correction bit; an error detection and correction unit of a memory that stores an output of the error correction selector; a data unit of the memory and the error detection and correction unit. An error detection and correction unit that checks data errors based on the output and corrects the errors; An information processing apparatus, comprising: a selector control unit that controls the error data selector and the error correction selector based on the presence or absence of an error in the error detection and correction unit. 4. A read data buffer for temporarily storing data read from a data section of the memory, a read error correction buffer for temporarily storing data read from an error detection and correction section of the memory,
The information processing apparatus according to claim 3, wherein the information processing apparatus is provided between the memory and the error detection and correction unit. 5. A memory control circuit for detecting and correcting a data error, comprising: a write buffer for temporarily storing write data from a system bus; and a write buffer for selecting one of the write data and the error-corrected data. A data selector, an error data selector for selecting one of the output of the write data selector and the read data, a data portion of a memory for storing an output of the error data selector, and an output data of the write data selector. An error correction generation unit that generates an error correction bit, an error correction selector that selects one of the error correction bit and the read correction bit, an error detection and correction unit of a memory that stores an output of the error correction selector, Read to temporarily store data read from the data part of the memory A data buffer, a read error correction buffer for temporarily storing data read from the error detection and correction unit of the memory, and a data error check based on outputs of the read data buffer and the read error correction buffer. A memory control circuit comprising: an error detection / correction unit that corrects an error; and a selector control unit that controls the error data selector and the error correction selector based on the presence or absence of an error in the error detection / correction unit.