JPH05282211A - Memory control circuit and fixed fault detecting circuit - Google Patents

Abstract

PURPOSE:To detect a single fault, and to early detect a fixed fault by rewriting normal data whose error is corrected an address in which the error occurs. CONSTITUTION:When the error which can be corrected is detected in a memory circuit to be controlled, it is communicated to an input terminal 7. A correction data feedback control circuit 1 allows an address holding circuit 2 to hold a reading address, a data holding circuit 3 to hold the normal data whose error is corrected, and syndrome holding circuit 11 to hold corrected correction data prepared by the memory circuit, address data indicating an error position, and a syndrome at that time. Then, the correction data feedback control circuit 1 stops an acceptance for the memory circuit, fetches the address and the data held by the address holding circuit 2 and the data holding circuit 3, outputs those data to the memory circuit, writes the corrected normal data in the address in which the fault occurs of the memory circuit, and updates the erroneous data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit and a fixed fault detection circuit for detecting or correcting a writing or reading error in a memory device.

[0002]

2. Description of the Related Art In a conventional memory control device, an error is detected when data is written in or read from a storage device, and if the error can be corrected, the error data is corrected and the correction is notified to a processor. Was.

[0003]

However, such a conventional device has a problem in that the data stored in the storage device keeps erroneous data until rewriting from the processor occurs. In addition, since it is merely to notify the host device or the external device whether or not the error that has occurred can be corrected, whether it is a single failure or not
There is a problem in that it is difficult to determine whether or not a fixed fault is present, and it takes time to detect the fixed fault.

The present invention has been made in view of such a situation, and is intended to detect a single fault and to detect a fixed fault at an early stage.

[0005]

In order to solve such a problem, the invention of claim 1 holds a corresponding address and an error-corrected normal data when an error-correctable error occurs. Means and a corrected data feedback control means for writing back normal data whose error has been corrected to the address where the error has occurred. According to a second aspect of the present invention, in the first aspect, the first holding means holds the syndrome for error correction, and the second holding means holds the syndrome rewritten and reread by the corrected data feedback control means. It is provided with a comparing means for comparing two syndromes and a holding notifying means for notifying the outside of the occurrence of a fixed failure when the comparison results match.

[0006]

According to the invention of claim 1, when an error held in the holding means occurs, the corrected data is written back to the corresponding address through the corrected data feedback control means. According to the second aspect of the present invention, the syndrome at the time of error correction and the syndrome rewritten and reread by the corrected data feedback control means are compared, and the fixed fault is detected by the comparison result.

[0007]

1 is a block diagram showing the configuration of a memory control device according to an embodiment of the present invention. This memory control circuit comprises a modified data feedback control circuit 1, an address holding circuit 2,
Data holding circuit 3, syndrome holding circuits 11 and 12,
It is composed of a comparison circuit 23 and input / output terminals 4 to 10, 13, and 24, and is installed between the memory circuit having the configuration shown in FIG. 2 and a host device or an external device.

When there is a read or partial write request from the host device or external device to the memory device, the address code and command of the access destination are supplied to the input / output terminals 4 and 6 of the modified data feedback control circuit 1. Then, it is output to the memory circuit through the input / output terminal 8 and the output terminal 10, and the data is read.

FIG. 2 shows a memory circuit controlled by the memory control circuit shown in FIG. 1. The error detection correction circuit 14 shown in FIG.
When the correctable error is detected at, the output terminal 20 notifies the input terminal 7 of FIG. 1 that the correctable error has occurred. Upon receiving this notification, the corrected data feedback control circuit 1 causes the address holding circuit 2 to hold the read address, the data holding circuit 3 to hold the normal data in which the error is corrected by the error detection / correction circuit 14, and the syndrome holding circuit. 11 stores the corrected data after the correction generated by the error detection / correction circuit 14, the address data indicating the error position, and the syndrome at that time. At this time, the syndrome is not held in the syndrome holding circuit 12.

The corrected data feedback control circuit 1 stores that the notification of the correction error is the first time, and stops the reception of the correction error from the host device or the external device to the storage device 15, and the address holding circuit 2 and the data holding are held. The address held in the circuit 3 and the data after error correction are fetched. Then, together with the write command generated by the modified data feedback control circuit 1, the data is output to the memory circuit from the address output terminal 8, the data output terminal 9, and the command output terminal 10, respectively, and after correction to the address where the failure of the storage device 15 has occurred. Normal data is written and the error data in the storage device 15 is updated.

When the correction data feedback control circuit 1 finishes updating the error data, the correction data feedback control circuit 1 outputs an address read command to read out the data of the address held in the address holding circuit 2, Output from 10 and read.

The read data is the error detection / correction circuit 1
In 4, the presence or absence of a fault is detected. At this time, if an error-correctable fault has occurred in the data, a correctable error is output from the output terminal 20. The correction data feedback circuit 1 receives this notification and memorizes that it is the second failure, and
Assuming that the failure has recurred, the syndrome holding circuit 12 outputs a holding signal generated by the error detection / correction circuit 14 to hold the syndrome indicating the error position, and the syndrome holding circuit 12 holds the syndrome. At this time, the syndrome holding circuit 11 holds the previous syndrome.

The syndrome comparison circuit 23 compares the syndrome holding circuits 11 and 12, and only when they match, notifies the corrected data feedback circuit 1 that the same fault has occurred.

As described above, when consecutive errors that can be corrected at the same bit position of the same address occur, it is regarded as a fixed fault, and when the corrected data feedback control circuit 1 receives the same fault notification, the higher-order device or the external device. The device is notified while holding the fixed failure notification, and the acceptance of the request to the storage device is started. At this time, the information of the address holding circuit 2, the data holding circuit 3, and the syndrome holding circuits 11 and 12 is still held in the holding control signal of the corrected data holding control circuit 1.

[0015]

As described above, the device of the present invention has the effect that the data at the address where the failure has occurred can be updated quickly with the corrected data without the intervention of another processor or the like. If a correctable failure occurs when the correctable failure occurs when reading the data at the same address in the next cycle in which the correctable failure occurs and when the data is updated, the syndromes of both are compared. Since a failure has occurred in the same bit position of, it is considered that a fixed failure has occurred and the failure information is retained and notified to the outside, so there is no external restriction and only the fixed failure can be promptly detected. It has the effect of being detectable.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory circuit that is a target for memory control and fixed fault detection by the circuit of FIG.

[Explanation of symbols]

 1 Corrected data feedback control circuit 2 Address holding circuit 3 Data holding circuit 11, 12 Syndrome holding circuit 23 Comparison circuit

Claims (2)

[Claims] 1. A memory control circuit that corrects and corrects an error when it is detected, and a holding means for holding a corresponding address and an error-corrected normal data when an error-correctable error occurs. By providing a correction data feedback control means for writing back the error-corrected normal data to the address in which the error has occurred, the error data due to a single failure is corrected and is quickly written to the storage device without the intervention of another processor. A memory control circuit characterized by the above. 2. The first holding means for holding the syndrome for error correction, the second holding means for holding the syndrome rewritten and reread by the corrected data feedback control means, according to claim 1, By providing the comparing means for comparing the two syndromes stored in the first holding means and the second holding means, and the notifying means for notifying the occurrence of the fixed failure to the outside when the comparison results match. A fixed-fault detection circuit capable of promptly notifying a host device or an external device of the occurrence of a fixed fault.