JPH05173899A - Information processor - Google Patents

Abstract

PURPOSE:To make the exchange of memory elements at the time of maintaining at a min. by correctly judging whether the fault of a control storing circuit in an information processor is the fixed fault or the intermittent one. CONSTITUTION:When data read out from the control storing circuit 1 is an error, the error is corrected by a correcting sign circuit 3 and the corrected data is stored in a corrected data storing circuit 5. At the same time, an error address is stored in an error address storing circuit 4. The data stored in the corrected data storing circuit 5 is read out again, it is judged whether the fault is the fixed one or the intermittent one in the control storing circuit by the state of the error and the result is stored in a judgement result storing circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control memory circuit in an information processing apparatus, and more particularly to a control memory circuit section in consideration of measures against failures.

[0002]

2. Description of the Related Art An output of a control memory circuit section is usually provided with an error correction code circuit (hereinafter referred to as "ECC circuit"). In this ECC circuit, if a read data error occurs even once, the data is automatically corrected and sent to the logic circuit of the next stage and is also reported as logging information, and the memory element in which the error occurred is replaced during the periodic maintenance. It was like this.

[0003]

In the conventional control memory circuit section, if a read data error occurs even once as described above, it is reported as logging information. Therefore, the memory element in which the error occurred is replaced during the periodic maintenance. It had been. In such a case, the RAM used for the control memory circuit element
There is a fixed failure that generates a fixed error and an intermittent failure that is seen as a soft error in the element.If it is a soft error, it is recovered by rewriting the correct data. Is unnecessary.
An object of the present invention is to solve the above-mentioned drawbacks, and to provide an information processing apparatus capable of accurately determining a failure of a control memory circuit and minimizing replacement of a memory element during maintenance.

[0004]

In order to achieve the above object, an information processing apparatus according to the present invention is an information processing apparatus having a built-in control storage circuit, wherein an address register circuit for sending an address to the control storage circuit and the control are provided. An error correction code circuit for inputting an output signal of the memory circuit, and a correction for correcting the error data by the error correction code circuit when the data read from the control memory circuit is error data and storing the corrected read data. A data storage circuit, an error address storage circuit for storing the error occurrence address, and a rewriting unit for rewriting the correction data in the correction data storage circuit storing the read data error,
And a determination result storage circuit for re-reading the data of the corrected data storage circuit to determine whether the control storage circuit has a fixed failure or an intermittent failure according to an error state and stores the determination result. Configured.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In this embodiment, the control memory circuit 1,
It comprises an address register circuit 2, an error correction code circuit 3, an error address storage circuit 4, a correction data storage circuit 5, a judgment result storage circuit 6, a counter circuit 7 and selection circuits 8 and 9.

The write data 101 is input to the selection circuit 9,
The write signal 102 is input to the control memory circuit 1, and the rewrite instruction signal 103 is input to the counter circuit 7 and the selection circuits 8 and 9. The address register circuit output signal 104 is input to the error address storage circuit 4 and the selection circuit 8, the output signals 105 and 106 of the selection circuits 8 and 9 are input to the control storage circuit 1, and the control storage circuit output signal 107 is the ECC.
Input to circuit 3. Further, the read data 108 which is the output signal of the ECC circuit 3 is sent to the correction data storage circuit 5 and the logic circuit of the next stage, and similarly the output signal 109 is the 1-bit error detection signal as the error address storage circuit 4 and the correction data storage circuit. 5 and the determination result storage circuit 6, and the output signal 110 of the counter circuit 7 is input to the error address storage circuit 4, the correction data storage circuit 5, and the determination result storage circuit 6. Further, the error address storage circuit 4
Output signal 111 of the correction data storage circuit 5 is input to the selection circuit 9, and an output signal 112 of the correction data storage circuit 5 is input to the selection circuit 9. Then, the output signal 113 of the determination result storage circuit 6 is sent to the logic circuit of the next stage as a determination result signal.

In the normal operation, that is, when the control memory circuit 1 is normal, the rewrite instruction signal 103 is "0" at the time of starting up the device, so that the selection circuits 8 and 9 have address registers. The write data 101 is selected and sent to the address indicated by the output signal 104 of the circuit 2, the write operation is executed at the timing of the write signal 102, and the contents of the firmware are written in the control storage circuit 1. Further, when the device is in operation, the control memory circuit 1 is only for reading, and the output signal 107 read from the control memory circuit 1 is input to the ECC circuit 3 according to the address indicated by the output signal 104 of the address register circuit 2. If there is no error, the 1-bit error detection signal 109 becomes "0" and at the same time the read data 108 is sent to the logic circuit of the next stage.

Next, the operation when a failure occurs in the control memory circuit 1 will be described. Output signal 107 of control storage circuit 1
Is input to the ECC circuit 3 and sent as read data 108 to the logic circuit of the next stage. However, when the data sent from the control memory circuit 1 has a 1-bit error, the read data 108 is correctly corrected and sent to the logic circuit of the next stage, but the 1-bit error detection signal 109 is detected. The output signal 104 of the address register circuit 2 at that time is also stored in the error address storage circuit 4 at the timing of the 1-bit error detection signal 109, and the read data 108 output after the 1-bit error is corrected by the ECC circuit 3 is output. It is stored in the corrected data storage circuit 5 at the timing of the 1-bit error detection signal 109.

By doing so, the address in which the 1-bit error occurs in the control memory circuit 1 is held in the error address memory circuit 4, and the correctly corrected data is held in the corrected data memory circuit 5. Become. When a 1-bit error occurs at a plurality of addresses, all error occurrence address values and corresponding data are stored in the error address storage circuit 4 and the correction data storage circuit 5, respectively. When the rewrite instruction signal 103 becomes active for the address in which the data read by the control memory circuit 1 has an error, the counter circuit 7 becomes active, and the error address memory circuit 4 and the corrected data memory circuit 5 are activated. Are simultaneously incremented (that is, the correction data corresponding to the error address are simultaneously incremented).

Therefore, the address and write data applied to the control memory circuit 1 are selected and sent out by the selecting circuits 8 and 9 as the error address memory circuit output signal 111 and the correction data memory circuit output signal 112.
Correctly corrected data is rewritten to the address where the error occurred in the past. Then, the re-read operation is executed for that address, and the control memory circuit output signal 1
Whether or not there is a failure in the memory element is detected by checking the error of 07 in the ECC circuit 3, storing the content of the 1-bit error detection signal 109 in the determination result storage circuit 6, and analyzing the output signal of the determination result signal 113. Can be determined. That is, if correct data is again written to each address of the control memory circuit 1 in which these 1-bit errors have occurred, and then the re-read operation is executed, if the re-read operation is no error, the past error is It can be determined that it is a soft error and it is not necessary to replace the memory element. Further, if an error occurs during re-reading, it can be determined that it is a fixed error and the memory element needs to be replaced. Therefore, the failure of the control memory circuit 1 can be accurately determined, and the replacement of the memory element can be minimized.

[0011]

As described above, the present invention provides a correction data storage circuit and an error address storage circuit which store correct read data and error address corrected by the ECC circuit when a read error occurs in the control storage circuit. A means that is built in and that has means for rewriting the correction data storage circuit data in the control storage circuit, and by reading again, determines whether the control storage circuit has a fixed failure or an intermittent failure, and stores the result. Therefore, it is possible to accurately determine the failure of the control storage circuit and minimize the replacement of the memory element during maintenance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing device according to the present invention.

[Explanation of symbols]

 1 ... Control memory circuit 2 ... Address register circuit 3 ... Error correction code circuit (ECC circuit) 4 ... Error address memory circuit 5 ... Corrected data memory circuit 6 ... Judgment result memory circuit 7 ... Counter circuit 8, 9 ... Selection circuit 101 ... Write data 102 ... Write signal 103 ... Rewrite instruction signal 104 ... Address register circuit output signal 105, 106 ... Select circuit output signal 107 ... Control memory circuit output signal 108 ... Read data 109 ... 1-bit error detection signal 110 ... Counter circuit output signal 111 ... Error address storage circuit output signal 112 ... Modified data storage circuit output signal 113 ... Judgment result signal

Claims (1)

[Claims] 1. An information processing device having a control memory circuit built-in, an address register circuit for transmitting an address to the control memory circuit, an error correction code circuit for inputting an output signal of the control memory circuit, and the control memory circuit. When the data read from is error data, the error data is corrected by the error correction code circuit, a corrected data storage circuit that stores the corrected read data, and an error address storage circuit that stores the error occurrence address, Rewriting means for rewriting the correction data of the correction data storage circuit storing the read data error, and whether the control storage circuit has a fixed failure depending on the error state by rereading the data of the correction data storage circuit. , A judgment result storage circuit for judging whether or not there is an intermittent failure and storing the judgment result, The information processing apparatus characterized by a.