JP3270367B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of distinguishing a recoverable error from an unrecoverable error.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the risk of developing uncorrectable errors due to accumulation of soft errors, when an error during a read operation from a semiconductor memory device can be corrected, an error detection and correction circuit is used. That is, the data that has been corrected is corrected, that is, a specific bit in the data bit group is inverted and rewritten.

As a first example, Japanese Patent Application Laid-Open No. Sho 63-27
In the storage control method described in "1555 Publication", when a central processing unit accesses a main memory, an error correction flag is set in a cache memory of a swap (store-in) method, and rewriting is performed at an address where the error correction flag is set. You are.

FIG. 3 is a block diagram showing a conventional storage control system for recovering a soft error by rewriting an error-correctable address in the cache memory. FIG. 4 is a block diagram showing the structure of the cache memory shown in FIG.

The operation of the above-described conventional storage control method will be described with reference to FIGS. 3 and 4. When a read operation is performed from the central processing unit 101 to the main memory 102, when the address does not exist in the address array 104, the read data is read from the main memory 102 and the error correction circuit 105
If the error is a correctable error, the corrected data is written to the cache memory 103, and the value of the address and the error bit (that is, the error correction flag) are written to the address array 104.

Here, assuming that the data is block 1, the address value is address 1, and the error bit is E1, the central processing unit 101 performs read and write operations on address 1 of the address array 104 while the operation is being performed. When the cache memory 103 is continuously accessed and a write is performed, the write bit W of the address array 104 is written.
1 is set.

When it becomes unnecessary for the central processing unit 101 to access the address, and data of another address in the main memory 102 becomes useful, that is, address 1 of the address array 104, that is, block 1 of the cache memory 103 When access to the memory is lost and it is no longer necessary to have the access there, the write bit W
If 1 is set, the value of the block 1 is written back to the main memory 102, and the value in the main memory 102 is updated to the value of the cache memory 103 and made to match.

At this time, when only reading from the cache memory 103 is performed by the central processing unit 101,
The value of the address 1 of the main memory 102 and the value of the block 1 are the same, and it is not necessary to perform rewriting. However, when the error bit E1 of the address array 104 is set, W
Even if “1” is not set, the value of the block 1 in the cache memory 103 stores the value after error correction.
Rewriting is performed on the address of the main memory 102 which has been in the error state.

As described above, when the correctable error is a soft error, the error is recovered by rewriting using the cache memory.

As a second example, Japanese Patent Application Laid-Open No. Hei 5-26669
In the semiconductor memory device described in "No. 2", when correcting output data for reading data from the memory cell array, in order to rewrite correct data to the cell, a read sense amplifier for the cell and an error bit correction circuit are provided. A register circuit for inverting the value of a bit is provided, and when an error occurs during output data correction at the time of reading, the error bit is inverted and rewriting is performed.

FIG. 5 is a block diagram showing the above-described conventional semiconductor memory device. FIG. 6 shows the column I / O circuit 213 of FIG.
FIG. 3 is a block diagram showing an / O circuit.

The operation of the above-described conventional semiconductor device will be described with reference to FIGS.

Memory cell array 201 of semiconductor memory device
When the read operation is performed, the read data is read by the sense amplifier 206, sent to the column I / O circuit 213 through the column gate 205, and sent to the error bit detection circuit 207.

If the read data is correctable data, the error bit detection circuit 207 selects the position of the erroneous bit of the data, and the column I /
The inversion signal T is sent to the data inversion unit 221 at the selected bit position in the O circuit 213, and the value of the bit in the data holding unit 222 is inverted.

Memory cell array 201 and sense amplifier 2
A bit signal line between the column I / O circuit 06 and the column gate 205 and the column I / O circuit 213 is bidirectional, and the data value of the column I / O circuit 213 after bit inversion, that is, error correction, is applied to the sense amplifier 206. Conveyed to. At this time, rewriting is performed on the memory cell array 201 by forcing the sense amplifier 206 to perform the writing operation.

As described above, when reading data from the memory cell array 201, the column I / O circuit 213 corrects the read data and outputs correct data.
Correct data is rewritten to the memory cell array 201 to recover from a soft error.

[0017]

A first problem is that a correctable error due to a soft error or the like occurs in the above-mentioned conventional storage control method or a semiconductor memory device, and the correctable error is a soft error. However, a correctable error can be recovered simply by a rewrite operation, but if a correctable error is caused by a memory cell defect, the error cannot be recovered by rewriting. It is an impossible error that cannot be prevented from stopping the failure of the semiconductor memory device.

The reason is that, for an address where an error has occurred, data corrected by an error detection and correction circuit, new updated data is rewritten, or the value of a correction bit is inverted by a cache memory swap method.
That is, only the corrected data is rewritten.

The second problem is that when rewriting is performed by the operation function of the cache memory, the effect of high-speed access is not obtained when the cache memory is mounted, not limited to the swap method, and the cache memory itself cannot be used. is there. The reason for this is that, for example, a technique for speeding up memory access in a supercomputer is to obtain read data at a speed almost close to the operation clock of the arithmetic unit when accessing a large-capacity memory composed of a large number of memory banks. This is because the operation of matching the contents of the cache memory with the contents of the memory cells is rather complicated in the cache memory for accelerating the memory access, and the function of increasing the speed cannot be exhibited. .

The third problem is that if rewriting is performed at the time of reading from a memory cell of a semiconductor memory device, for example, in a supercomputer of a parallel multiple processor shared memory type, discontinuity occurs when continuous reading of high-speed large-volume data. Cycles occur and control becomes complicated. The reason is that at the time of reading from the memory cell of the semiconductor memory device, when an error is corrected and rewritten,
In the case of a type in which the memory cell is destroyed at the time of reading, the configuration is such that the memory cell always rewrites,
The continuous operation of the read / write cycle is continued, and there is no disturbance in timing. However, if the memory cell is not destroyed at the time of reading, only when a correctable error occurs, the rewriting operation of the corrected data is added during the continuation of the continuous operation of the reading cycle. This is because the read cycle is not maintained, the read cycle uniformity is not maintained, and the flow of pipeline control for high-speed processing becomes discontinuous.

The degree of integration of the memory elements of a semiconductor memory device has been improved, and the miniaturization of memory cells has been progressing more and more in the future, and the chances of occurrence of soft errors or correctable errors due to defective memory cells have been increasing.

A first object of the present invention is to reduce the load of manufacturing technology for improving the reliability of a memory element itself, the operation check heat run, screening, etc. for preventing bit errors of the memory element, and to reduce the load on a semiconductor memory. Replaces the address portion where a bit error has occurred in the device by the function equivalent to the function of the cache memory, tolerates some memory cell failures, and prevents the semiconductor memory device from going down even if memory cell failures occur frequently It is to be.

A second object of the present invention is to reduce maintenance downtime by eliminating a method of replacing all memory cell boards as a maintenance measure for early resolution of a semiconductor memory device down due to a memory cell failure, It is to reduce the labor of the user.

[0024]

According to a first semiconductor memory device of the present invention, a data storage unit having a plurality of memory cells;
An error detection / correction circuit that detects whether an error exists in the data read from the memory cell of the data storage unit and generates a correction data if the error is correctable; and possess the correction data alternate cache unit for storing the address corresponding to the data to a dedicated, the correction data alternate cache unit, the revised
A cache data register for storing positive data,
Cache data that stores the address corresponding to the correction data
And the cache directory comprises:
In the address of the memory cell corresponding to the correction data,
Is set to ON when writing is performed again.
Rewrite flag, and the rewrite flag is turned on.
Read the address of the set memory cell.
In the event that data overflows, the same bit can be corrected again.
Error is detected by the error detection / correction circuit.
And a rewrite recurrence flag that is set to

A second semiconductor memory device according to the present invention is the first semiconductor memory device, wherein the error detection / correction is performed.
Corrected from the correct circuit and the corrected data replacement cache unit
Information indicating whether the error is correctable or uncorrectable,
Error address, error bit position, rewrite
Errors, including rewrite and rewrite flags
Enter information and output as error logging data.
Error data register.

A third semiconductor memory device according to the present invention is the first or second semiconductor memory device, wherein a central processing unit is provided.
Operation commands and writing from the host device represented by the device
Data and read / write data
An input data register; and
The operation command is decoded and the data storage unit and
And command to be output to the correction data replacement cache unit
A decoder and write data from the input data register.
Error correction bits to detect errors for data
Error check to create and output to the data storage unit
Character generation circuit and reading from the data storage unit
At this time, the data is stored in the corrected data replacement cache unit.
Exists and the rewrite flag for that data
Is off, the data from the data storage unit is replaced.
Instead, the data from the corrected data replacement cache unit
Output data register to output to the request source.
I do.

[0027]

[Operation] The semiconductor memory device of the present invention uses the corrected value of data at the address where a correctable error has occurred as a substitute for a memory cell by a cache function. From the side, reading can always be performed continuously at a constant timing.

That is, the present invention can be effectively used for connection to an access device in which it is difficult to employ a cache memory, or for access devices in which it is difficult to control timing disturbance due to writing during continuous read operation.

In the case other than a correctable error due to a soft error which is recovered by rewriting, the writing of the address is stopped permanently and replaced with a cache data register, thereby preventing the semiconductor memory device from stopping. The operating rate can be easily increased.

[0031]

Next, an embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a block diagram showing the configuration of the semiconductor memory device of the present invention. Referring to FIG. 1, a semiconductor memory device according to the present invention includes an input data register, a command decoder 2, an error check character generation circuit 3, a data storage unit 4, a correction data substitute cache unit 10, an error detection / correction unit. A circuit 19, a read data register 20, and an error data register 2
And 1.

The input data register 1 stores operation commands sent from a central processing unit or an input / output processing unit of a computer, ie, commands for write / read operation, write data at the time of writing,
Write / read address is received. The command decoder 2 determines the operation of the memory control unit 6 for controlling the operation of the data storage unit 4 and the operation of the cache directory 12 based on the operation command in the input data register 1.

The error check character generation circuit 3
In the case of a write command, a correction code bit for detecting an error at the time of reading and detecting a bit position of a correctable error is generated for the write data.

The data storage unit 4 includes a memory writing circuit 5
, Memory control unit 6, address decoder 7, and memory cell 8
The write data to which the correction code bit is added by the error check character generation circuit 3 is written to the address of the memory cell 8 specified by the address decoder 7 by the write address of the input data register 1. Remember.

In the case of a read command, the correction data replacement cache unit 10 sends the contents of the address specified by the address decoder 7 to the error detection / correction circuit 19 via the memory read circuit 9 in accordance with the read address of the input data register 1. At the time of reading, if the error is a correctable error, the value of the read address itself at which the error occurred is stored, and the address specified by the cache directory 12 that generates the address of the cache data register 16 is stored in the address. The read data corrected by the error detection / correction circuit 19 is stored in the cache data register 16 through the cache writing circuit 11.

The correction data replacement cache unit 10
Is an address directory 1 indicating a storage address which is a function of the cache itself in the cache directory 12.
5, when a new rewrite is performed on an already existing address, a rewrite flag 14 indicating that the location at that address has been rewritten, and the rewrite flag 14 At the time of re-reading the address, or when a correctable error occurs,
It has a rewrite recurrence flag 13 indicating that it is other than a soft error, and a rewrite recurrence error detection circuit 18 for flag control.

In the case of a read command, when the read address in the input data register 1 already exists in the cache directory 12, the output data register 20 is read from the corrected data substitute cache unit 10 through the cache read circuit 17. The data is sent back to the central processing unit or the input / output processing unit of the computer device.

The error data register 21 obtains error information from the error detection / correction circuit 19 and the rewrite reoccurrence error detection circuit 18, and detects the address where the error occurred, the syndrome, ie, the correction bit position, and the error in the rewrite. The recovered soft error is distinguished from errors other than the soft error when the correctable error occurrence bit position occurs at the same position after rewriting, and together with the error occurrence address, the central processing unit of the computer device,
Alternatively, it reports to the maintenance diagnosis processing processor.

Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart showing the operation of the semiconductor memory device of the present invention. Referring to FIG. 2, the semiconductor device of the present invention first comprises:
The command decoder 2 analyzes the operation command of the access data from the central processing unit or the input / output device of the computer device received by the input data register 1,
Whether it is read or write (step S2 in FIG. 2)
1) Determine the operation.

If the determination of the operation (step S1 in FIG. 2) is a read operation, it is checked whether or not the address to be read exists in the address directory 15 of the cache directory 12 (step S2 in FIG. 2). If so, it is checked whether the rewrite flag 14 is turned on (step S9 in FIG. 2).

When the rewrite flag 14 is not turned on (step S9 in FIG. 2), a correctable error has occurred once, but error recovery in the rewrite operation by the access device, ie, the central processing unit or the input / output device. Since the process is not performed, it means that the error is being replaced in the correction error replacement cache unit 10, and the data is read from the cache data register 16 (step S10 in FIG. 2) and returned and output to the access source device (FIG. 2). Step S8) is performed.

When the rewrite flag 14 is ON (step S9 in FIG. 2), the error recovery process in the rewrite operation is performed by the access device after a correctable error has occurred once, so that the cache data Although data exists in the register 16, the memory cell 8 is read in order to know whether or not the error has been recovered by rewriting (step S11 in FIG. 2).

Reading the memory cell 8 (step S1 in FIG. 2)
1) When no error has occurred (step S1 in FIG. 2)
2) means that the error has been recovered by the rewriting operation from the access device, and the error data replacement in the correction data replacement cache unit 10 becomes unnecessary, so the corresponding address of the cache data register 16 is cleared ( FIG. 2 step S15). When the memory cell 8 is read (step S11 in FIG. 2) and an error occurs (step S12 in FIG. 2), if the error is not correctable (step S13 in FIG. 2), the semiconductor memory device performs a degeneration operation or stops. (Step S6 in FIG. 2).

When the error can be corrected (step S in FIG. 2)
13) The rewrite reoccurrence error detection circuit 18 checks whether the error occurrence bit position is the same as the previously generated error (step S14 in FIG. 2), that is, whether it is the same syndrome. S14)
The rewrite flag 13 of the cache directory 12 is turned on (step S16 in FIG. 2) to indicate that the error is other than a soft error, and the data corrected by the error detection / correction circuit 19 is stored in the cache data register 16 And sends it to the output data register 20 (step S7 in FIG. 2), and returns it as read data to the access device (step S8 in FIG. 2).

If the error bit position is not the same as the previously generated error (step S14 in FIG. 2), even though the rewriting has been performed by the access device,
Since an error occurred at another bit at the same address,
It is also considered that a soft error has occurred, and the data corrected by the error detection / correction circuit 19 is written to the cache data register 16 and sent to the output data register 20 without setting the rewrite recurrence flag 13 (step S7 in FIG. 2). The data is returned and output as read data to the access device (step S8 in FIG. 2).

When the address to be read does not exist in the address directory 15 of the cache directory 12 (step S2 in FIG. 2), the data in the memory cell 8 is read (step S3 in FIG. 2). The operation is performed.

That is, the memory cell 8 is read, an error check is performed by the error detection / correction circuit 19, and if no error occurs (step S4 in FIG. 2), the data of the memory cell 8 is returned and output as read data to the access device. (Step S8 in FIG. 2).

When an error occurs (step S4 in FIG. 2), when the data can be corrected, the data corrected by the error detection / correction circuit 19 is cached in order to perform a primary replacement in the corrected data replacement cache unit 10. The data is written to the data register 16 and sent to the output data register 20 (step S7 in FIG. 2), and is returned and output as read data to the access device (step S8 in FIG. 2).

Reading the memory cell 8 (step S2 in FIG. 2)
3) When an error occurs (step S4 in FIG. 2),
If the error cannot be corrected (step S5 in FIG. 2), the semiconductor memory device performs the degenerate operation or stops (step S6 in FIG. 2).

If the operation determination (step S1 in FIG. 2) is not a read operation, that is, if it is a write operation, it is checked whether an address to be written in the address directory 15 of the cache directory 12 exists (step S19 in FIG. 2). If it exists, it is checked whether the rewrite recurring flag 13 is turned on (step S20 in FIG. 2).

When the rewrite reoccurrence flag 13 is ON (step S20 in FIG. 2), a correctable error has occurred once in the past, and despite the fact that rewriting has been performed by the access device, the same error occurs during reading and again. Since a correctable error has occurred in the address and the bit position, it is possible that the memory cell 8 has a defect other than the soft error. Therefore, the data in only the corrected data replacement cache unit 10 is updated (step S23 in FIG. 2), and the memory cell 8 is updated. Is not written, and the replacement in the correction data replacement cache unit 10 is continued, thereby preventing the degradation or stop of the semiconductor memory device due to an uncorrectable error due to the accumulation of defects in the memory cell 8 (step S6 in FIG. 2).

If the rewrite reoccurrence flag 13 is not on (step S20 in FIG. 2), it is determined whether the rewrite flag 14 is on (step S21 in FIG. 2) and the rewrite flag 14 is turned on (step S20 in FIG. 2). In the case of S21), that is, the rewriting is performed once by the access device, and a correctable error occurs again at that address, but the bit position of the error is the same as the previous one (step S2 in FIG. 2).
14) is not the case and the soft error has occurred in another bit at the same address, so that the memory cell 8
The data is written to the memory (step S24 in FIG. 2), and the error is recovered by rewriting.

If the rewrite flag 14 is not on (step S21 in FIG. 2), only a read operation from the access device is performed since a correctable error has occurred in the past, that is, the write operation has been performed once. Therefore, the rewrite flag 14 of the cache directory 12 is turned on (step S22 in FIG. 2), data is written to the memory cell 8 (step S24 in FIG. 2), and error recovery by rewriting is performed.

Then, the error detection / correction circuit 19 and the rewrite reoccurrence error detection circuit 18 turn on the rewrite flag 14 together with the address where the error has occurred, the bit position, and the syndrome as maintenance information (step S22 in FIG. 2). State and Degeneration or Stop of the Semiconductor Memory Device Due to the ON State of the Rewrite Recurrence Flag 13 (Step S16 in FIG. 2) and Uncorrectable Error (Step S16 in FIG. 2)
6) The state is collected, set in the error data register 21 (step S17 in FIG. 2), and output to the access device or the maintenance diagnostic processor (step S18 in FIG. 2).

[0055]

The first effect of the present invention is that the error recovery processing by rewriting a soft error can be performed without disturbing the timing of the pipeline operation following the pipeline operation of the arithmetic unit. It can be used as a main memory of a large-capacity, multi-bank arithmetic processing device in a supercomputer device. The reason is that the register circuit is much faster than the semiconductor memory device,
This is because the replacement of the error portion of the memory cell and the rewriting operation for preventing the accumulation of the soft error are performed by the writing operation of the new data of the access device, so that the operation of the pipeline is not disturbed.

The second effect is that the redundancy of the semiconductor memory device is increased and reliability is improved by replacing the correctable error portion of the memory cell with a cache memory function. The reason is that the correctable error portion of the memory cell is replaced, some degree of defect of the memory cell element is tolerated, and the initial failure of the semiconductor memory device and the lot defect of the element product are performed in the actual operation state after the shipping inspection. This is because the device can be prevented from being down, and the interval between the parts replacement stoppage of the defective portion due to the preventive maintenance can be extended.

A third effect is that maintainability is improved by making it possible to distinguish between soft errors and other correctable errors. The reason is that a rewrite flag and a rewrite recurring flag are provided in the directory part of the correction data replacement cache section so that it is possible to prevent the parts from being replaced for the purpose of preventing unnecessary troubles. This is because the computer device for replacement can be stopped, and the number of man-hours for component replacement and the cost of components can be reduced.

The fourth effect is that by incorporating the error part replacement function by the cache memory function in the vicinity of a memory chip or a data storage unit, a memory element, a storage circuit, or a storage device having no apparent soft error can be obtained. By doing so, it is possible to reduce the processing load of error logging, reduce the communication cost of automatic reporting of error logging information, and reduce the number of error analysis steps.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional storage control method.

FIG. 4 is a block diagram showing a structure of the cache memory of FIG. 3;

FIG. 5 is a block diagram showing a conventional semiconductor memory device.

FIG. 6 is a block diagram showing an input / output circuit with a data inversion function in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input data register 2 Command decoder 3 Error check character generation circuit 4 Data storage part 5 Memory writing circuit 6 Memory control part 7 Address decoder 8 Memory cell 9 Memory reading circuit 10 Correction data substitution cache part 11 Cache writing circuit 12 Cache directory 13 Re Write recurrence flag 14 Rewrite flag 15 Address directory 16 Cache data register 17 Cache read circuit 18 Rewrite recurrence error detection circuit 19 Error detection / correction circuit 20 Output data register 21 Error data register 101 Central processing unit 102 Main storage 103 Cache memory 104 Address array 105 Error correction circuit 201 Memory cell array 205 Column gate 206 Sense amplifier 20 7 Error bit detection circuit 213 I / O circuit 221 Data inversion unit 222 Data holding unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 G06F 11/10 G06F 12/16

Claims (3)

(57) [Claims] 1. A data storage unit having a plurality of memory cells, and detecting whether an error exists in data read from the memory cells in the data storage unit. Error detection
And correcting circuit, wherein the correction data and the address corresponding to the correction data possess the correction data alternate cache unit to be stored in a dedicated, the correction data alternate cache unit, before
A cache data register for storing the correction data,
A cache for storing an address corresponding to the correction data;
And a cache directory.
Is the address of the memory cell corresponding to the correction data.
Set on when data is rewritten
Rewrite flag to be turned on and the rewrite flag
Address of the memory cell set to
Can be corrected again to the same bit when read out
Function error is detected by the error detection / correction circuit.
And a rewrite recursion flag set to on
A semiconductor memory device characterized by the above-mentioned. 2. The error detection / correction circuit and the correction
Whether the error can be corrected from the primary data replacement cache unit
Information indicating whether it is uncorrectable, the address where the error occurred
Address, error bit position, rewrite flag, and
Enter the error information including the rewrite
-Error data register to output as logging data
2. The semiconductor memory device according to claim 1, comprising:
Place. 3. A host device represented by a central processing unit.
Operation commands, write data, and write / read
An input data register for storing read data;
Decoding the operation command from the input data register.
The data storage unit and the corrected data replacement cache
A command decoder for outputting to the queue section, and the input data
Detect errors in write data from the registers
Error correction bits for the data storage unit
An error check character generation circuit to be output;
When reading from the data storage unit, substitute the corrected data
Data exists in the cache unit and the data
If the rewrite flag is off, the data
Instead of the data from the storage unit, the corrected data replacement key
Select the data from the cache section and output it to the request source.
2. A power data register comprising :
Or the semiconductor memory device according to 2.