JPS63271555A - Storage control system - Google Patents

Abstract

PURPOSE:To prevent soft errors from being accumulated by storing error corrected data in a cache memory when data read out of a main memory has an error, setting the error bit of an address array and rewriting the data in the main storage when a block is substituted. CONSTITUTION:If the data read out of the main storage 2 has an error and the error is correctable, the data corrected by an error correcting circuit 5 is stored in, for example, a block 1 of the cache memory 3 and the error bit E1 of the address array 4 is set. Then when the block 1 becomes an object of rewriting, the data in the block 1 is written in the main storage 2 on condition that a write bit W1 is set, but the data is written in the main storage 2 similarly even when the error bit E1 is set. Consequently, correct data is written in an address from the cache memory 3 without fail and soft errors are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to rewriting of error correction data, and particularly to a rewriting method using an intermediate memory.

(Prior Art) Recent advances in LSI technology have dramatically increased the degree of integration of memory elements, which has led to miniaturization of memory cells, making it impossible to ignore the problem of soft errors in main memory. Soft errors are not caused by physical destructive failures, but can be recovered by rewriting the data.

Therefore, if an error correction code is added to the data, soft errors can be corrected, and since they are not physical destructive failures, no special measures should be taken, or they can be corrected when reading data from main memory. A known method has been used to prevent the accumulation of soft errors by correcting and immediately rewriting when a soft error exists.

(Problem to be Solved by the Invention) In the conventional method described above, even if a soft error occurs in the former case, the data in the main memory does not contain the soft error unless new write data is written. However, there is a drawback that there is a large risk that uncorrectable errors will occur due to the accumulation of soft errors.

On the other hand, in the latter case, a special circuit is required to write the corrected data into the main memory again, which has the disadvantage that the amount of hardware increases and the control becomes complicated.

An object of the present invention is to include, in addition to a main memory, a thousand memory which is divided into a plurality of blocks, and an address array storing address information corresponding to each block of the memory, and an address array IC error bit area. established,
If the data read from the main memory contains errors, the error-corrected data is stored in the memory and transferred to the central processing unit, and at the same time the error bit in the address array is set, and the block in question is replaced. The object of the present invention is to provide a storage control system which eliminates the above drawback by writing data back to the main memory if one error bit is set in the event of an error, and which suppresses the increase in hardware.

(Means for Solving the Problems) A storage control system according to the present invention includes a main memory, a main memory, an address array, a central processing unit, and an error correction circuit.

The main memory is for storing data added with an IAb correction code, and the cache memory is for storing data divided into a plurality of blocks using a swap method.

The address array is for storing address information including error bits corresponding to each block of the muyash memory.

A central processing unit is connected to the cache memory and address array for processing information.

When the error correction circuit reads data from the main memory, there is a memory access from the central processing unit due to an error bit to indicate that error correction has been performed. If there is a correctable error in the read data when reading the block, the error is not corrected and the data is stored in the cache memory and transferred to the central processing unit, and at the same time, the error bit in the address array is set. This is for writing back to the main memory if the error bit is set when the data is replaced.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the storage control system according to the present invention. In FIG. 1, 1 is a central processing unit, 2 is a main memory, 3 is a 100% memory, 4 is an address array for indicating address information of data on the middle memory 3, and S is correctable to read data from the main memory 2. This is an error correction circuit that corrects any errors that may occur.

As shown in FIG. 2, the cache memory 3 is divided into four blocks, and the address array 4 contains the address information of each block of the plain memory 3 and whether or not each block has been written to by the central processing unit 1. It is composed of write bits WO to W3 for indicating whether data read from main memory 2 has been corrected, and error bits EO to E3 for indicating whether or not error correction has been performed on data read from main memory 2.

In the swap (store-in) system memory 3, when the central processing unit 1 writes to an area existing on the cache memory 3, the data is written only to the cache memory 3 and not to the main memory 2. Not included.

However, if the address accessed from the central processing unit 1 does not exist on the cache memory 3, data is read from a new area of the main memory 2 to any block of the cache memory 3; In the block where writing was being performed, writing to the main memory 2 continues at the same time.

The present invention focuses on the operation in which the data of the block that has been written is written to the main memory 2, and when there is an error in the data read from the main memory 2 and the error can be corrected, It is assumed that data that has not been corrected by the error correction circuit S is stored in, for example, block 1 of the cache memory 3, and at the same time, the error bit E1 of the address array 4 is set. Next, when block 1 becomes the target of rewriting, if the write bit (Wl) is set, the data of block 1 will be written to main memory 2, but the same applies even if the error bit E1 is set. Data is written to main memory 2.

Therefore, even if a soft error occurs in the main memory 2, if the address where the soft error occurred is read and the error can be corrected, correct data will always be written to that address from the main memory 3. The soft error will disappear.

(Effects of the Invention) As explained above, the present invention includes, in addition to the main memory, a thousand memory that is divided into a plurality of blocks, and an address array that stores address information corresponding to each block of the middle memory. In preparation, an error bit area is provided in the address array, and if there is an error in the data read from the main memory, the error-corrected data is stored in the cache memory and transmitted to the central processing 'A' location. The error bit of the array is set and the block in question is 1.
If the error bit is set when the software is replaced, by writing all the data to the main memory, it is possible to rewrite the address where the soft error occurred with a very small amount of additional hardware. The effect of completely preventing the accumulation of errors is Chiru.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the storage control method according to the present invention. FIG. 2 is a block diagram showing an example of implementing a storage control method according to the prior art. 1...Central processing unit 2...Main memory 3...Middle memory 4...Address array S...Error correction circuit

Claims (1)

[Claims] A main memory for storing data with an error correction code added, a cache memory for storing data divided into a plurality of blocks using a swap method, and a main memory for storing error bits corresponding to each block of the cache memory. an address array for storing address information including; a central processing unit connected to the cache memory and the address array for processing information; and a central processing unit for performing error correction when reading data from the main memory. The error bit indicates that there is a memory access from the central processing unit, there is no data in the cache memory, and there is a correctable error in the read data when the data is read from the main memory. and the error-corrected data is stored in the cache memory and transferred to the central processing unit, and at the same time, an error bit in the address array is set, and when the block is replaced, the error bit is set. and an error correction circuit for writing back to the main memory.