JP3178913B2 - Semiconductor file device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash type EEPROM.
The present invention relates to a semiconductor file device using an OM as a memory, and more particularly to error correction of write data.

[0002]

2. Description of the Related Art In a semiconductor file device using a flash EEPROM as a memory, a controller writes data to an erase block assigned to the flash EEPROM while verifying the data. When a verify error occurs during the verification of the write data, the controller performs the following error processing. That is, after making the erase block in which the error has occurred unusable, the controller writes data to be written to this erase block to another erase block. In this case, the above-described error processing must be performed every time a write error occurs at the time of the above-described verification, and it takes time to write data. The block is made unusable and a new erase block must be used.
However, there is a drawback that the use efficiency of the material is remarkably deteriorated.

[0003]

In a semiconductor file device using a flash EEPROM as a memory as described above, an erase block in which a verify error has occurred at the time of writing data is disabled and the data is transferred to another erase block. Error processing such as writing must be performed, and there is a drawback that the use efficiency of the flash EEPROM is significantly deteriorated.

Accordingly, the present invention eliminates the above-mentioned drawbacks and eliminates the use of erase blocks that cannot be used when a verify error occurs during data writing, thereby significantly improving the use efficiency of a flash EEPROM. It is intended to provide a file device.

[0005]

According to the present invention, a flash EEPROM is provided as a memory.
In a semiconductor file device for writing data to a PROM while verifying data by a controller, in addition to an area for writing data to the flash EEPROM, there is provided a redundant area for writing error information relating to a verify error generated when writing the data, And verifying means for verifying data to be written to the flash EEPROM on the controller side;
Address detecting means for detecting a write destination address in the flash EEPROM of data having an error as a result of verification by the verifying means; and an address detected by the address detecting means as error correction information of the flash EEPROM. Error information writing means for writing the data in the redundant area while verifying the data; and reading data from the address at which an error has occurred based on the error correction information written in the redundant area when reading data from the flash EEPROM. And an error correction means for rewriting to "".

[0006]

According to the semiconductor file device of the present invention, error information relating to a verify error generated when writing this data is written in a redundant area provided in a flash EEPROM. The verifying means on the controller side verifies data to be written into the flash EEPROM. The address detecting means detects a write destination address in the flash EEPROM of the data in which the verification result of the verifying means has become an error. The error information writing unit writes the address detected by the address detection unit as error correction information in the redundant area of the flash EEPROM while verifying the address. The error correcting means is the flash type E
When reading data from the EPROM, the data at the address where the error has occurred is rewritten to "0" based on the error correction information written in the redundant area.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the semiconductor file device of the present invention. 1 is a flash type E inside
The semiconductor memory chip 2 constituting the EPROM is composed of a flash type E
A controller that reads and writes data from and to the EPROM. The controller 2 includes a CPU 21 for comprehensively controlling the operation of the controller, an R / W control circuit 22 for performing data read / write control on the semiconductor memory chip 1, a verify circuit 23 for verifying write data in 1-bit units, When a verify error occurs, an error information writing circuit 24 that writes error information to a redundant area B provided at the end of a write area in units of pages constituting each block of the flash EEPROM,
It has a data reproducing circuit 25 for reproducing and reading data having a verify error at the time of reading into correct data, and a page memory 26 for temporarily storing data before writing. Note that the flash EEP in the semiconductor memory chip 1
The ROM is divided into a 512-byte data write area A and a 40-byte redundant information write area B for writing error information.
A 12-byte data write area A and a 40-byte redundant area B form a 552-byte page write area for one page, and n such page write areas for one page are collected. One erase block is formed.

Next, the operation of this embodiment will be described. Upon receiving one page of write data from the information processing system (not shown), the CPU 21 of the controller 2 temporarily stores the write data in the page memory 26. Then the CPU
21 reads out the one page of write data from the page memory 26 and converts the write destination logical address received from the system side into a physical address on the semiconductor memory chip 1 side, and then converts these to the R / W control circuit 22. Give to. The R / W control circuit 22 writes the data in a page area in the erase block of the semiconductor memory chip 1 specified by the physical address. At this time, the verify circuit 23 reads out the data for one page written in the semiconductor memory chip 1 in units of 1 bit via the R / W control circuit 22 and stores the data stored in the page memory 26 before writing. A verify operation is performed in which the data is compared with 1-bit data, and the data is again written to the semiconductor memory chip 1 until the two match. However, the verify circuit 23
Means that even if the above verify operation is repeated a predetermined number of times,
If the bit data does not match the corresponding one-bit data before writing, the address where the verify error has occurred is sent to the error information writing circuit 2 via the CPU 21.
Inform 4

The error information writing circuit 24 writes an address in the semiconductor memory chip 1 in which the verify error has occurred into a redundant area B in a page writing area having this address. However, the verifying circuit 23 also performs verification on the error information written in the redundant area B by the error information writing circuit 24. When the operation of the error information writing circuit 24 described above is completed, the CPU 21 operates the verifying circuit 23 again to verify the write data of the next bit. In this manner, when the verification of the written data of one page in 1-bit units and the writing of the error information (address at which the verification error has occurred) in the case where the verification error has occurred are completed, the CPU 21 sends the next page from the system side. Is obtained and temporarily stored in the page memory 26 to repeat the same write operation as described above. Thus, data is written in the data storage area A in each page writing area of the erase block of the semiconductor memory chip 1, and error information is written in the redundant area B.

Next, when the CPU 21 receives a read command from the system (not shown), it converts the read logical address given at the same time into a physical address of the memory chip 1, and then converts this to a semiconductor memory chip from the R / W control circuit 22. 1 to perform an operation of reading data. At this time, when the R / W control circuit 22 reads data from the data storage area A in the page write area specified by the address, it temporarily stores the data in the page memory 26. Thereafter, the error information is read from the redundant area B in the page write area and passed to the data reproducing circuit 25. When the data reproducing circuit 25 sequentially corrects 1-bit data in the page memory 26 indicated by the applied error information, that is, the write address of the data in which the verify error has occurred, to "0", it notifies the CPU 21 of this. Upon receiving this notification, the CPU 21 reads the data in the page memory 26 and transfers it to the system side.

Here, each erase block of the flash EEPROM in the semiconductor memory chip 1 is erased before data is written, and all the blocks become "1".
Therefore, it means that the data which causes a verify error at the time of verify at the time of data writing could not be set to “0”. That is, the address becomes “0” when data writing to a certain address is successful, and becomes “1” when data writing is not successful. Therefore, when the data reproducing circuit 25 knows the address at which the verify error has occurred, the correct data that should have been written to that address is determined to be "0", and the semiconductor memory stored in the page memory 26 as described above. The error correction of the read data can be performed only by rewriting the address portion where the verify error of the data read from the memory chip 1 has occurred to “0”.

According to this embodiment, when an error occurs at the time of one-bit verification at the time of data writing,
An address that specifies the location where the verify error has occurred in 1-bit units is written as error information in a redundant area b provided in a page write area of an erase block of the semiconductor memory chip 1, and this data is read when the data is read. The error correction of the read data can be performed only by reading the address written in the redundant area B and rewriting the read data specified by the address to “0”. Therefore, when a verify error occurs as in the prior art, there is no need to make the erase block or the like in which the error occurs unwritable.
The efficient use of the PROM becomes possible.

In addition, as a process for correcting an error at the time of the above-described verification, an error correction of read data can be performed by simply replacing an address portion given as error information with "0" at the time of data reading. Therefore, the error correction process is simple, and the load on the controller 2 is reduced, and the reading and writing of data can be performed at high speed. Moreover, in this example, since the redundant area B for writing the error information is provided continuously to the data write area A in the same page, after reading the data from the data write area A, Without splitting)
Since error information in the redundant area B can be read, data can be read at a higher speed than in a case where the redundant area is provided in another place. The redundancy area B may be provided at any place in the flash EEPROM if the speed at the time of reading data is sacrificed.

FIG. 2 is a diagram showing a second embodiment of a configuration in which a redundant area is provided in a flash EEPROM constructed in the semiconductor memory chip 1 described above. In this example, a 40-byte redundant area B is provided at the first part of the page write area, and a 512-byte data storage area A is provided following this. Therefore, the 40-byte redundant area B and the 512-byte data storage area A constitute a page write area of one page, and eight pages constitute one erase block. In this embodiment, similarly to the previous embodiment, the data is written in the data write area A, and the error information, which is the address information of the error that occurs at the time of verification performed in 1-bit units when writing the data, is at the top of the same page. Is written to the redundant area b in the portion of. Thereafter, when reading the data, first, error information is read from the redundant area B at the beginning of the read page, and then the data is read out from the data storage area A provided following this area. Each time the data is read, the data in which a verify error has occurred can be rewritten to "0" and sequentially read, in contrast to the error information that was read first. Therefore, the error correction can be performed before all the data is read, so that the read data can be output in the order in which the data was read and the error was corrected, and the data reading speed was further increased as compared with the previous embodiment. It can be fast.

FIG. 3 is a diagram showing a third embodiment of a configuration in which a redundant area is provided in a flash EEPROM constructed in the semiconductor memory chip 1 described above. The erase block of this example has eight data storage areas A of 512 bytes for one page, and a 512-byte redundant area B of one page is added to the bottom of these data storage areas A. One erase block is formed by the data storage area A of eight pages and the redundant area B of one page. Other configurations are the same as those of the previous embodiment shown in FIG. In this example, when a verify error occurs at the time of one-bit unit verification at the time of data writing, the address information where the verify error has occurred is temporarily stored in the memory on the control side, and the data is stored in the data storage area of the eight pages. Until all are written while verifying as described above.
Similarly to the above, the address where the verify error has occurred is stored in the memory on the control side. When the data is written in all the data storage areas of the eight pages, the address information having a verify error stored in the memory on the control side is collectively written to the redundant area B.

According to this embodiment, the writing of the error information into the redundant area B is not time-divided for each page.
Data writing can be performed faster than in the previous embodiment. Moreover, since it is expected that the error information of the page allocated to the redundant area B is generally small, the page having the largest number of defects can be initially set. Therefore,
Since another page having few defects can be allocated to the data write area, the probability of occurrence of a verify error can be reduced and the data write speed can be increased. When reading data from the flash EEPROM, first, the error information written in the redundant area B is read, and then the data is read from the data storage area A based on the already read error information. By rewriting the erroneous address to “0”, error correction can be performed while sequentially reading data. For this reason, it is possible to sequentially output data for which error correction has been completed before not reading out all data, and to read out data accordingly. Further, the page having the largest number of defects during use can be replaced with the redundant area B, and effective measures can be taken against uneven distribution of defects during use.

In the above embodiment, when a verify error occurs, the error information is transmitted to the semiconductor memory chip 1.
The write processing is performed on the redundant area B provided in the memory. If a verify error occurs when the error information is written, the entire erase block having the redundant area B is set to be unwritable, and all data is written to another. A process of rewriting to an erase block must be performed. But,
In this case, there is a disadvantage that the erasure block must be replaced due to an error generated when writing a small amount of error information, and the memory area is not effectively used.
The fourth embodiment described below is for avoiding such a disadvantage.

FIG. 4 is a diagram for explaining a fourth embodiment of the present invention. This figure is used when error information is written in a redundant area allocated after or before each page of an erase block as shown in FIG. 1 or FIG. 2, or allocated to the last page of an erase block as shown in FIG. FIG. 8 is a diagram showing an example of a format for writing error information used when writing error information in a given redundant area. That is, in addition to an error location address where an error has occurred at the time of verification performed at the time of writing data and an area for writing normal data that is correct data to be written to the error location address,
A blank area for writing information indicating a failure in writing error information is provided. The redundant area b, when writing the address of the error location and the normal data, if a verify error occurs in any of the writing, invalidates both data and replaces predetermined invalid information with a blank attached. After writing, the error location address and the normal data where the writing failed are written to another location in the redundant area b. If a verify error occurs again while this error information is being written to the another location again, the same is repeated. Even if such a process is repeated, if even one bit fails to write the error information in the redundant area B, the data written in the entire page is invalidated, and the error information is written in another page. Perform processing to rewrite all data including the data.

At the time of reading the above error information, if invalid information is written in a blank attached to the area where the error information is written, the error information written immediately before this blank is invalidated. Then, by using error information in which invalid information is not written in the blank, for example, an error correction process similar to that of the embodiment shown in FIG. 1 is performed, and data is read.
By the way, when writing the error information, only the writing of the normal data fails and the error location address is correctly written, as another measure, the error location address and the normal data are stored in another place of the redundant area b. Is written again. On the other hand, if there are two error location addresses when reading the error information, it is possible to determine that the error location address written later and the normal data following the error location are valid. In this case, the blank address shown in FIG. There is no need to write invalid information to the server. In this embodiment, the error location address and the regular data are adopted as the error information. However, as in the embodiment shown in FIG. 1, the same effect can be obtained by using only the error location address as the error information. Both writing and reading of data can be speeded up.

By the way, when the error information is written in the error information format of {(error location address), (regular data), (blank)} × n as described above, the frequency of occurrence of an error occurring at the time of writing the error information When is low, the probability that invalid information is written to a blank for writing data indicating that the error information is invalid is extremely low, and the invalid information writing area allocated as the blank is not used and is wasted, This has the disadvantage that the memory area is not used effectively. Therefore, a fifth embodiment for avoiding the above-mentioned disadvantage will be described below. In this example, as a write format of the error information, as shown in FIG.
(Error location regular data)｝ × n is adopted. When writing error information in such a format, the writing of the error information itself fails, that is, when a verification error occurs in any of {(error location address) and (regular data)} and writing fails , Both of the error information are invalidated. By the way, since the flash EEPROM can be erased only in units of erase blocks, it is impossible to erase the invalidated error information after all. Therefore, when the writing of the error information itself has failed, the following processing is performed in this example without changing the erase block itself having the redundant area B in which the error information has been written.

That is, the contents of the management table for converting the logical block address of the data write destination provided from the system side to the physical block address are rewritten, and the replacement erasure is different from the erasure block in which the writing of the error information has failed. After the logical block address corresponds to the block, a process of writing all the data to be written to the original erase block to the replacement erase block again is performed. Also in the case of this example, at the time of data reading, the data can be corrected by replacing the data at the corresponding address with correct data and reading the data in accordance with the error information.

According to this embodiment, when a verify error occurs when error information is written in the above-described format in the redundant area b attached to the erase block to which data is to be written, the entire erase block is discarded. Since the data to be written to the abandoned erasure block can be written again to the replacement erasure block, invalid information indicating that the writing of the error information itself has failed from the format for writing the error information is written. Since the region (blank) can be omitted, the flash type EEPROM is compared with the fourth embodiment.
The OM memory area can be used effectively.

By the way, in all of the above-described embodiments, in addition to the writing of the data storage area A, the writing of the redundant area B must be performed in a time-sharing manner, and the writing is required twice. There was a disadvantage. Therefore, it may be requested that the writing be completed only once.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention, which has been made in consideration of the above-mentioned problems. 1 is a semiconductor memory chip which internally constitutes a flash EEPROM, 2 is the semiconductor memory chip 1
It is a controller that reads and writes data from and to a flash EEPROM configured therein. Controller 2
, Which comprehensively controls the control operation of this controller
PU 21, R / W control circuit 22 for performing write / read control of data with respect to semiconductor memory chip 1, verify circuit 23 for verifying write data in 1-bit units, page memory 26 for temporarily storing data before writing
And an ECC processing circuit 27 that performs ECC processing on the read data to correct the data. Note that the flash EE included in the semiconductor memory chip 1
A plurality of erase blocks (1) to (4) are allocated to the PROM.

Next, the operation of this embodiment will be described. Upon receiving the write data from the information processing system (not shown), the CPU 21 of the controller 2 adds ECC information to the write data and temporarily stores the data in the page memory 26 as data for one page. Thereafter, the CPU 21 reads out the one page of write data from the page memory 26, converts a logical block address to which the data specified by the information processing system is written, into a physical block address, and The write data is passed to the R / W control circuit 22. As a result, the R / W control circuit 22 writes the data of one page in the erase block in the semiconductor memory chip 1 specified by the physical block address.

At this time, the verify circuit 23 converts the data of one page written in the semiconductor memory chip 1 into R /
The data is read out one bit at a time in the verify mode via the W control circuit 22, compared with the corresponding one-bit data before writing stored in the page memory 26, and the data is stored in the semiconductor memory chip 1 until they match. A verify operation for rewriting is performed. However, if the data read in the verify mode does not match the corresponding data before writing even after repeating the verify operation a predetermined number of times, the verify circuit 23 notifies the CPU 21 of the address where the verify error has occurred, Then, the process proceeds to the verification of the next bit. When the verification for one page is completed, the CPU 21 refers to the data before writing stored in the page memory 26 at the address where the verify error has occurred, and checks the number and distribution of the errors. If the error correction can be performed in the range, the writing of the data for one page is completed, and the process proceeds to the data writing process for the next page.

If the CPU 21 determines that this data cannot be corrected to the correct data by the ECC processing based on the number of errors in the data of one page and the distribution thereof, the CPU 21 separates the logical block address into another. After replacing the erase block at the write destination with the substitute erase block, control is performed to write all the data to be written into the abandoned erase block into the substitute erase block. The CPU 21 counts the number of remaining replacement erase blocks each time such replacement of the erase block is performed, and when the remaining becomes small, performs a process of notifying a system (not shown) that the life of the file device has expired. .

Next, when reading data from the semiconductor memory chip 1, the CPU 21 converts the read logical address given from the system side to a physical address and then gives it to the R / W control circuit 22. Thereby, the R / W control circuit 22
Reads data from the erase block at the given read address, but the read data is
Send to 7. Even if there is an error in the read data, the ECC processing circuit 27 outputs the read data to the CPU 21 after performing ECC processing on the read data and correcting it to correct data. The CPU 21 transfers the read data corrected by the ECC processing circuit 27 to an information processing system (not shown).

According to the present embodiment, even if an error occurs in the verification performed when data is written to the erase block in the semiconductor memory chip 1, if the error can be saved by the ECC processing, the data remains unchanged. To complete writing, the frequency of occurrence of replacement of erase blocks is reduced and the memory area is effectively used, compared to a conventional semiconductor file device having no redundant area, which replaces erase blocks when one error occurs. Can be used. or,
If an error that cannot be rescued by the ECC processing occurs, the erase block at the write destination is replaced. However, when the remaining erase block for replacement is reduced, the system side is notified that the life of the file device is over. Thus, it is possible to prevent a scandal in which data can no longer be written because the life of the file device suddenly expires.

[0030]

As described above, according to the semiconductor file device of the present invention, when a verify error occurs during data writing, an unusable erase block is prevented from appearing, so that the use efficiency of the flash EEPROM is significantly improved. Can be enhanced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor file device of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a third embodiment of the present invention.

FIG. 4 is a diagram showing a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory chip 2 ... Controller 21 ... CPU 22 ... R / W control circuit 23 ... Verify circuit 24 ... Error information writing circuit 25 ... Data reproduction circuit 26 ... Page memory 27 ... ECC processing circuit A ... Data writing area B … Redundant area

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 17/18 G11C 29/00

Claims (4)

(57) [Claims] 1. A flash EEPROM as a memory
In a semiconductor file device for writing data to the flash EEPROM while verifying data by a controller, in addition to an area for writing data to the flash EEPROM, error information related to a verify error generated when writing the data is written. Verify means for providing a redundant area and verifying data to be written into the flash EEPROM on the controller side, and a write destination in the flash EEPROM for data having an error as a result of verification by the verify means; Address detecting means for detecting an address; and an address detected by the address detecting means as error correction information.
Error information writing means for writing while verifying the redundant area of the PROM, and the flash EEPROM
An error correcting means for rewriting data at an address where an error has occurred to "0" based on the error correction information written in the redundant area when data is read from the semiconductor file device. . 2. A flash memory according to claim 1, wherein a redundant area provided in said flash EEPROM is provided after a data write area in which data of one page is written.
A semiconductor file device as described in the above. 3. A flash memory according to claim 1, wherein a redundant area provided in said flash EEPROM is provided before a data write area in which data of one page is written.
A semiconductor file device as described in the above. 4. A flash memory according to claim 1, wherein a redundant area provided in said flash EEPROM is allocated to said arbitrary one page data write area in an erase block composed of n page data write areas. Item 2. The semiconductor file device according to Item 1.