JPH0223442A - Memory control device - Google Patents

Memory control device

Info

Publication number
JPH0223442A
JPH0223442A JP63174777A JP17477788A JPH0223442A JP H0223442 A JPH0223442 A JP H0223442A JP 63174777 A JP63174777 A JP 63174777A JP 17477788 A JP17477788 A JP 17477788A JP H0223442 A JPH0223442 A JP H0223442A
Authority
JP
Japan
Prior art keywords
memory
error
rewriting
control device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63174777A
Other languages
Japanese (ja)
Inventor
Tatsuro Hashiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63174777A priority Critical patent/JPH0223442A/en
Publication of JPH0223442A publication Critical patent/JPH0223442A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To relieve the intermittent error by showing the effectiveness of data with effective information when the error is detected at the data read from a cache memory and making ineffective the block of a memory when the rewriting information shows non-rewriting.
CONSTITUTION: When an error is detected at the data read from a memory control device 1 having a cache memory 2 and when it is shown that the data of the entry to generate an error by the effective information and the rewriting information of the address array of the memory 2 are effective and the rewriting is not executed, the entry is made ineffective. The rewriting of the memory 2 is executed by the data from a main memory 3. Consequently, when the error is intermittent, the error is recovered and the continuation of the processing can be performed by the re-writing of the memory 2. Thus, a memory control device to be able to relieve the intermittent error of the cache memory is obtained.
COPYRIGHT: (C)1990,JPO&Japio
JP63174777A 1988-07-13 1988-07-13 Memory control device Pending JPH0223442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63174777A JPH0223442A (en) 1988-07-13 1988-07-13 Memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63174777A JPH0223442A (en) 1988-07-13 1988-07-13 Memory control device

Publications (1)

Publication Number Publication Date
JPH0223442A true JPH0223442A (en) 1990-01-25

Family

ID=15984486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63174777A Pending JPH0223442A (en) 1988-07-13 1988-07-13 Memory control device

Country Status (1)

Country Link
JP (1) JPH0223442A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033976A (en) * 1993-08-11 2000-03-07 Sony Corporation Ohmic electrode, its fabricating method and semiconductor device
JP2012178121A (en) * 2011-02-28 2012-09-13 Nec Computertechno Ltd Information processor and error correction support method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56117400A (en) * 1980-02-20 1981-09-14 Fujitsu Ltd Buffer memory control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56117400A (en) * 1980-02-20 1981-09-14 Fujitsu Ltd Buffer memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033976A (en) * 1993-08-11 2000-03-07 Sony Corporation Ohmic electrode, its fabricating method and semiconductor device
JP2012178121A (en) * 2011-02-28 2012-09-13 Nec Computertechno Ltd Information processor and error correction support method

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