JPH0223442A - Memory control device - Google Patents

Abstract

PURPOSE:To relieve the intermittent error by showing the effectiveness of data with effective information when the error is detected at the data read from a cache memory and making ineffective the block of a memory when the rewriting information shows non-rewriting. CONSTITUTION:When an error is detected at the data read from a memory control device 1 having a cache memory 2 and when it is shown that the data of the entry to generate an error by the effective information and the rewriting information of the address array of the memory 2 are effective and the rewriting is not executed, the entry is made ineffective. The rewriting of the memory 2 is executed by the data from a main memory 3. Consequently, when the error is intermittent, the error is recovered and the continuation of the processing can be performed by the re-writing of the memory 2. Thus, a memory control device to be able to relieve the intermittent error of the cache memory is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Summary 1 The present invention relates to a memory control device, and more particularly to error handling in a memory control device that employs a store-in type cache memory.

Traditionally, in this type of memory control device, when an uncorrectable error occurs in the store-in cache memory, the data in the cache memory where the error occurred is left as is and the requesting device retries. was going on.

Here, the store-in method requires new contents of the main storage device, and if there is no free space in the cache memory, the contents of the cache memory are returned to the storage device described in 1. This involves writing the contents of the main memory device into the area, and since the data is usually rewritten on the cache memory, the contents of the cache memory and the contents of the main memory device do not necessarily match.

In such conventional memory control devices, even if an error occurs in the cache memory, the error remains and the requesting device is retried, resulting in the error being detected again as a result of the retry. There is a drawback.

Aims and Objectives The present invention has been made to eliminate the drawbacks of the conventional devices as described above, and an object of the present invention is to provide a memory control device capable of relieving intermittent errors in a cache memory.

Composition of the Invention A memory control device according to the present invention includes a storage means for storing validity information indicating whether data stored in a cache memory is valid or not, and rewriting information indicating whether the data has been rewritten; a detection means for detecting an error in data read from the cache memory; and the valid information corresponding to the data in which an error has been detected by the detection means indicates that the data is valid, and the rewrite information indicates that the data has not been rewritten. and means for invalidating the block of the cache memory in which the data is stored.

X1ヱNext, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 9, a memory control device 1 according to an embodiment of the present invention has a store-in type cache memory 2,
It is connected to the arithmetic processing device 5 and the input/output processing device 6, and controls access to the main storage device 3 from the arithmetic processing device 5 and the input/output processing device 6.

The cache memory 2 is a copy of the main memory W3, but when the cache memory 2 becomes full and new data from the main memory 3 is written, a certain unit (block) of the cache memory 2 is transferred to the main memory W3. Data is read and written on the cache memory 2 until it is written back to fi2.

Therefore, the contents of cache memory 2 and main memory 3
The content does not necessarily match.

FIG. 2 is a block diagram showing the configuration of the cache memory 2 of FIG. 1. In the figure, the cache memory 2 includes a data array 21 that stores memory data, and a data array 21 that indicates whether the memory data stored in the data array 21 is valid or invalid.
an address array 22 that stores memory addresses and control information consisting of bits and M bits that indicate whether the memory data has been rewritten; and an error detection circuit 23 that detects errors in memory data read from the data array 21. , a read address register 24 , a read data register 25 , and a write data register 26 .

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

The arithmetic processing unit 5 or the input/output processing unit 6 is the main storage device 3
When memory data stored in is required, a read request is output to the memory control device 1.

The memory control device 1 refers to the cache memory 2 in response to this read request, and if there is no hit in the cache memory 2, that is, whether the V bit of the address array 22 corresponding to the entry for which the read request was made is 0'° or Alternatively, if the memory addresses do not match, the requesting device (processing unit 5 or input/output processing unit 6) retrieves the memory data from the main storage device 3 and replaces the memory data in the cache memory 2. The memory data is transferred to.

By referring to the cache memory 2 in response to a read request,
If there is a hit in the cache memory 2, the memory data in the cache memory 2 is transferred as is to the requesting device.

If an error is detected by the error detection circuit 23 in the process of reading memory data stored in the cache memory 2, the error detection circuit 23 notifies the requesting device of the occurrence of the error and also sends an error message to the failure processing device 4. Make a processing request. It should be noted that the request source device similarly issues an error processing request to the failure processing device 4.

After receiving this error processing request, the fault processing device 4 collects fault information and then obtains the entry number of the cache memory 2 in which the error occurred from the fault information.

Fault handling device 4 then uses read address register 24 and read data register 25 to obtain control information from the entry in address array 22 .

Of this control information, the ■ bit is always "1" since the cache memory 2 is hit, but the M bit is undefined. At this time, the failure processing device 4 refers to the M bit, and invalidates the entry if the M bit is 0''.

That is, if the memory data corresponding to the entry has not been rewritten, the write data register 26 is used to clear the control information of the entry.

After the entry is invalidated by the failure processing device 4,
A retry of the requesting device occurs. As a result of this retry, the entry is accessed again, but since the entry is invalidated, there is no hit in the cache memory 2, and the cache memory 2 is rewritten with the memory data from the main storage device 3. .

If the error detected by the error detection circuit 23 is an intermittent error, the error is recovered by this rewriting operation of the cache memory 2, and processing can be continued.

In this way, when an error occurs in the cache memory 2 in the memory control device 1 having the cache memory 2 that adopts the store-in method, the memory data of the entry where the error occurred is valid according to the V bit and M bit of the address array 22. If the error detected by the error detection circuit 23 is an intermittent error, the cache memory 2 Since the error is recovered by the rewrite operation, it is possible to continue the process. Therefore, intermittent errors in the cache memory 2 can be relieved.

As explained above, according to the present invention, when an error is detected in data read from the cache memory, the validity information stored corresponding to the data indicates the validity of the data, When the rewriting information indicates that the data has not been rewritten, the cache memory block in which the data is stored is invalidated, thereby making it possible to relieve intermittent errors in the cache memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of the cache memory shown in FIG. 1. Explanation of symbols of main parts 1...Memory control device 2...Cache memory 3...Main storage device 4...Fault processing device 21... ...Data array 22...Address array 23...Error detection circuit

Claims (1)

[Claims] (1) A storage means for storing validity information indicating whether the data stored in the cache memory is valid or not and rewrite information indicating whether the data has been rewritten or not; a detecting means for detecting an error; and when the valid information corresponding to data in which an error has been detected by the detecting means indicates that the data is valid and the rewriting information indicates that the data has not been rewritten, the data is stored. and means for invalidating a block of the cache memory.