JPS60225941A - Microprogram control device - Google Patents

Abstract

PURPOSE:To make an erroneous data ineffective by executing write to a control memory, and thereafter, setting a block effective bit in a word in an address array in which control information is written in accordance with its data block, to ''0'', when a fault is occurred in a write data. CONSTITUTION:A tilted device detects the generation of a parity error of an address register 2, an address array write data register 3, a control memory write data register 4, etc., holds the contents of the address register 2 by an output of an OR gate 11, and clears the address array write data register 3. At the same time, this device sets a write pulse control register 5, writes ''0'' in control information in an address array 6, and clears a V bit. Also, it inhibits write to the subsequent control memory 7 and the address array 6, therefore, the write pulse control register 5 is cleared by an output of a flip-flop 9 which is holding the output of the OR gate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device in a data processing device, and more particularly to a fault handling method for a write control circuit to a control memory thereof.

(Prior Art) Conventionally, in this type of microprogram control device, the control memory is used as a buffer memory for the main memory.

The fault handling method used in such devices is to write data to which a parity bit has been added in advance to the control memory, and when reading the contents of the control memory, a parity check is performed on the readout data to detect faults. δ was.

When a fault is detected, a flag is set to indicate that the microinstruction is invalid, so that the fault does not affect the hardware activated by the microinstruction output from the control memory. At the same time, the data block containing the faulty microinstruction in the control memory was disabled. However, with the above method, the data written to the control memory may fail.
If this happens, there is a possibility that incorrect data may be written. To prevent this, it is necessary to detect the above write data failure and control the write data so that it is not written to the control memory, but if the control memory has a large capacity and writing is performed at high speed, Since the delay time of one circuit is large, such control has become impossible.

When erroneous data is written to the control memory, the following two problems occur.

First, when a fault is detected in data read from the control memory, it is impossible to distinguish whether the fault is in the control memory itself or in the written data. Therefore, even though it is a write data failure,
A block of control memory has been disabled.
Ta.

Second, as already explained, if a fault is detected in the data read from the control memory, a flag is set to disable the microinstruction, but after this flag is set, the hardware There was a certain delay time required before the data was referenced, and during that time there was a possibility that the hardware would perform unrecoverable operations.

Regarding the method of using the above-mentioned control memory as a buffer memory of the main memory, Japanese Patent Application No. 57-15
96r Microprogram Control System".

(Object of the Invention) An object of the present invention is to detect a fault in the write data to the control memory, and to respond to the data block containing the write data after the write data has been written to the control memory. The above problem is solved by writing again to set the block valid bit in the word inside the address array in which the control information is written to 6, and invalidating the error data inside the data block. An object of the present invention is to provide a microprogram control device configured to perform the following steps.

(Structure of the Invention) A microprogram control device according to the present invention includes a main memory, a control memory, and an address array.

It is constructed and equipped with an address register, a comparator, a write control circuit, a fault detection means, and an auxiliary control means. ``Main memory is for storing multiple microinstructions.

The control memory is for holding some of the microinstructions read from main memory.

The address array is for holding management information regarding data blocks contained in the control memory.

The address register is for holding read and write addresses of the control memory and address array.

The comparator compares addresses in order to detect whether or not a target microinstruction exists on the control memory.

If the target microinstruction does not exist on the control memory, the write control circuit reads the microinstruction belonging to the data block from the main memory and writes it to the control memory, and also writes control information regarding the data block to the address array. It is for writing.

The failure detection means is for detecting when a failure occurs in the write data provided by the write control circuit.

The auxiliary control means detects that the data block is valid within a ninth address array that holds control information for the data block included in the write data when an error is detected in the write data by the failure detection means. This is to invalidate the data block in which faulty data has been written by clearing the bit indicating that the fault has occurred.

(Actual flow side) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention. In FIG. 1, l is a write control circuit, 2 is an address register, 3 is an address array write register, 4 is a control memory write data register, 5 is a write J pulse control register, 6 is an address array, 7 is a control memory, 8 is the main memory, 9 is a flip-flop, 10 is a comparator, and 11.12 are each OR.
It is a gate.

In an eleventh example showing an embodiment of the present invention, the main memory 8 stores microinstructions. The control memory 7 functions as a buffer memory for the main memory 8, and holds a portion of the microinstructions in pre-divided blocks.

Address array 6 holds unit word management information for one block in control memory 7.

Address register 2 provides read and write addresses to control memory 7 and address array 6. Control memory write data register 4 supplies write data to control memory 7. Address array write data register 3 supplies write data to address array 6. Write pulse control register 5 controls 1 write pulses to control memory 7 and address array 6 .

The comparator 10 compares the block address included in the management information in the address array 60 table with the upper bits of the address register 2 to determine whether the target microinstruction exists as data in the control memory 7. Then it is detected by and. OR gate 11 is connected to address register 2
, address array write data register 3, and control memory write data register 4. The flip 70 knob 9 holds the output of the OR game) 11. The write control circuit 1 includes a data bus between the main memory 8 and the control memory write data register 4, and supplies write data to the control memory 7.
Control means are provided for providing appropriate data to address register 2, address array write data register 3, and write pulse control register 5. The OR gate 12 is an OR gate with the write control signal from the write control circuit l.
11) and gives this to the write pulse control register 5.

Next, the operation of the circuit of this embodiment will be explained in detail. Address register 2 stores the address of the next microinstruction to be executed.
When set, the microinstruction corresponding to the address given (by the lower bits of the control memory 7 and the seat address register 2) is read out. At the same time, control information corresponding to the data block containing the microinstruction is read from the address array 6. The control information in the address array 6 is in the format shown in FIG. Detect whether or not it has been read.

Here, if the result of the above comparison does not match 12 or if the V bit is 0, the read microinstruction is treated as invalid and a new 1% target data block is read from the main memory 8. Then, it writes to the control memory 7 and sends an instruction to the control circuit 1. Upon receiving the instruction, the write control circuit 1 reads the microinstruction of the target data block from the main memory 8 and sets it in the control memory write data register 4.

At one time, the write control circuit 1 sends new control information regarding the block to the address array write data register 3.
Set the write address to address register 2, and write the write control signal to write pulse control register 5.
to set.

The above processing is repeated until writing of microinstructions for one data block is completed.

However, if an @ sign occurs in the data stored in any of the address register 2, address array write data register 3, and manufacturing unit memory write data register 4 during this time, the invalid data will be stored in the control memory 7, and address array 6, creating problems as in the prior art.

In order to solve this problem, the present invention clears the V bit in the control information in the address array 6 to 0 in response to a data block in which invalid data has been written. Specifically, the OR gate 11 detects that a parity error has occurred in any of the address registers 2, 7, the address register 2, 7, the write data register 3, and the control memory write data register 4. The contents of the address register 2 are held and cleared to the contents i and o of the address array write data register. At the same time, by setting the write pulse control register 5, 0 is written to the control information in the address array 6, and the V bit is cleared to O. Further, in order to prohibit future writing to the control memory 7 and address array 6, the contents of the write pulse control register 5 are cleared to 0 by the output of the tritubular flop 9 holding the output of the OR gate 11. A timing chart of the above operation is shown in FIG.

(Effects of the Invention) As explained above, the present invention has the advantage that when invalid data is written to the control memory and address array, the contents of the corresponding data block are invalidated, thereby preventing the invalid microinstruction from occurring. This has the effect of preventing execution.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially illustrating an embodiment of a microprogram control device according to the present invention. FIG. 2 is a diagram showing the format of data stored in the address array. FIG. 3 is a timing chart showing the operation of the microprogram controller shown in FIG. It is. 1...Write control circuit 2...Address register 3...Address array write data register 4...
Control memory write data register 5...Write pulse control register

Claims (1)

[Scope of Claims] A main memory for storing a plurality of microinstructions, a control memory for holding a part of the plurality of microinstructions read from the main memory, and data contained in the control memory. An address array for holding management information regarding the block, an address register for holding the control memory as well as read addresses and write addresses of the address array, and a target microinstruction on the control memory. a comparator for comparing addresses for the purpose of detecting whether the target microinstruction is present in the control memory; and if the target microinstruction does not exist in the control memory, reading out the microinstruction belonging to the data block from the main memory). and write it to the control memory. a write control circuit for writing control information regarding the data block into the address array; and failure detection means for detecting a failure in the write data provided by the write control circuit. , when an error is detected in the write data by the fault detection means, the data block is and auxiliary control means for invalidating the data block in which the faulty data has been written by clearing a bit indicating that the faulty data is valid. Microprogram controller.