JPS58169253A - Error detection system - Google Patents

Error detection system

Info

Publication number
JPS58169253A
JPS58169253A JP57052058A JP5205882A JPS58169253A JP S58169253 A JPS58169253 A JP S58169253A JP 57052058 A JP57052058 A JP 57052058A JP 5205882 A JP5205882 A JP 5205882A JP S58169253 A JPS58169253 A JP S58169253A
Authority
JP
Japan
Prior art keywords
read
data
parity
read information
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57052058A
Other languages
Japanese (ja)
Inventor
Keiichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052058A priority Critical patent/JPS58169253A/en
Publication of JPS58169253A publication Critical patent/JPS58169253A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

PURPOSE:To detect a fault of a parity checking means itself and to improve the reliability of read information by changing over a parity check on the read information to an even or odd parity check according to the state of bits of a read address. CONSTITUTION:Data is stored previously in a memory M together with an added parity bit P which shows whether the number of ''1''s in the data is even or odd and the memory contents are read successively according to addresses from an address register AR. The read data is applied through a data register DR to a parity checking circuit PC, whose parity checking result is supplied to one input of an exclusive OR gate EX. Further, read bits of the register AR are applied to a switching circuit SEL, whose output is supplied to the other input of the gate EX. Then, the even or odd parity check on the read information is made selectively and the output of the gate EX is applied to a setting and a resetting circuit R and S to detect a fault of even the parity checking circuit PC itself, improving the reliability of the read information.
JP57052058A 1982-03-30 1982-03-30 Error detection system Pending JPS58169253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052058A JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052058A JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Publications (1)

Publication Number Publication Date
JPS58169253A true JPS58169253A (en) 1983-10-05

Family

ID=12904208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052058A Pending JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Country Status (1)

Country Link
JP (1) JPS58169253A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473722B1 (en) 1997-12-18 2002-10-29 Nec Corporation Compact fault detecting system capable of detecting fault without omission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473722B1 (en) 1997-12-18 2002-10-29 Nec Corporation Compact fault detecting system capable of detecting fault without omission

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