JPS58169253A - Error detection system - Google Patents

Error detection system

Info

Publication number
JPS58169253A
JPS58169253A JP57052058A JP5205882A JPS58169253A JP S58169253 A JPS58169253 A JP S58169253A JP 57052058 A JP57052058 A JP 57052058A JP 5205882 A JP5205882 A JP 5205882A JP S58169253 A JPS58169253 A JP S58169253A
Authority
JP
Japan
Prior art keywords
read
parity
parity check
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57052058A
Other languages
Japanese (ja)
Inventor
Keiichi Kato
恵一 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052058A priority Critical patent/JPS58169253A/en
Publication of JPS58169253A publication Critical patent/JPS58169253A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

PURPOSE:To detect a fault of a parity checking means itself and to improve the reliability of read information by changing over a parity check on the read information to an even or odd parity check according to the state of bits of a read address. CONSTITUTION:Data is stored previously in a memory M together with an added parity bit P which shows whether the number of ''1''s in the data is even or odd and the memory contents are read successively according to addresses from an address register AR. The read data is applied through a data register DR to a parity checking circuit PC, whose parity checking result is supplied to one input of an exclusive OR gate EX. Further, read bits of the register AR are applied to a switching circuit SEL, whose output is supplied to the other input of the gate EX. Then, the even or odd parity check on the read information is made selectively and the output of the gate EX is applied to a setting and a resetting circuit R and S to detect a fault of even the parity checking circuit PC itself, improving the reliability of the read information.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は、メモリよ抄読み出した情報の誤り検出方式ｋ
係り、特にバリティ検査方式に於いて、その信頼性を更
Ｋ向上させることが可能な誤り検出方式に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention The present invention provides an error detection method for information read out from a memory.
In particular, the present invention relates to an error detection method that can further improve the reliability of a parity check method.

《２》技術の背景 あらかじめ用意されたマイクロプログラムによクて情報
制御装置を制御するマイクロプログラム制御方式で社、
前記マイクロプログラムは読み出し専用メモリＫ記憶さ
れ、制御の進行にと亀なって読み出される。この様ＫＬ
て読み出されたマイクロプログラムの妥当性を検査する
方式の一つとしてパリティ検査方式がある。《2》Background of technology
The microprogram is stored in a read-only memory K and read out as the control progresses. Like this KL
A parity check method is one of the methods for checking the validity of a microprogram read out.

かかるパリティ検査方式は取り扱う１グループのデータ
中の＠１′の数が偶数（偶数パリティ検査）又は奇＆（
奇数パリティ検査）となる様Ｋパリティピットを付加し
て共にメモリに記憶させておき、読み出しの際に所定の
バリティになるか否かを艙査してビット誤りを検出する
方式である。This parity check method is used when the number of @1' in one group of data is even (even parity check) or odd &(
In this method, K parity pits are added and stored together in the memory so as to perform an odd parity check (odd parity check), and bit errors are detected by checking whether or not a predetermined parity is achieved when reading.

（８）従来技術の問題点 第１図は従来のパリティ検査方式を適用したメモリ装置
のブロック図である。図中、Ｍはメモリ、ＤＥＣはアド
レスデコーダ、ＤＲはデータレジスタ、ＡＲはアドレス
レジスタ、ＰＣはハリティ検査圓路、▲Ｂはアドレスバ
ス、ＤＢはデータパス、ＥＯはエラー信号である。(8) Problems with the Prior Art FIG. 1 is a block diagram of a memory device to which a conventional parity check method is applied. In the figure, M is a memory, DEC is an address decoder, DR is a data register, AR is an address register, PC is a harness check circuit, ▲B is an address bus, DB is a data path, and EO is an error signal.

この様なメモリ装置に於いてメモリＭには、あらかじめ
ｌデータ中の１１６の数が偶数又は奇endpage:1 数になる様にパリティビッ｝Ｐが付加された形で記憶さ
れており、アドレスレジスタＡＲかもあたえられたデー
タに従ってメモリ内容が順次読み出される。読み出され
たデータはパリティ検査回路ＰＣでパリティチ．ツタが
行われ、読み出されたデータにビット誤抄がないか検査
される。In such a memory device, a parity bit P is added to the memory M so that the number 116 in l data becomes an even number or an odd number, and the address register AR The memory contents are sequentially read out according to the supplied data. The read data is parity checked by the parity check circuit PC. A check is performed to check whether there are any bit errors in the read data.

しかしながら、この様な誤抄検出方式では、パリティ検
査回路ＰＣ自体のある種の故障モードでは、読み出し情
報の誤９が検出できないことがある。例えば、奇数パリ
ティ検査を行っていてデータレジスタＤＢのパリティが
偶数パリティとなった時に−１−レベルのエラー信号Ｅ
Ｏを発生する様な場合に、パリティ検査回路ＰＣの故障
でその出力ＥＯが雪０１レベルに固定されてしまった場
合には、読み出し情報が常に正しいと見なされてしｔ−
、誤り検出ができなくな９てしまり。However, with such an erroneous paper detection method, the error 9 in the read information may not be detected in certain failure modes of the parity check circuit PC itself. For example, when an odd parity check is performed and the parity of the data register DB becomes an even parity, the -1- level error signal E
If the output EO is fixed at the snow 01 level due to a failure in the parity check circuit PC, the read information will always be considered correct.
, error detection becomes impossible and ends up being 9.

またパリティ検査自身社読み出しアドレスと何ら関連を
もたなーため、パリティが正しいとしても所廖のアドレ
スから読み出されているという保証はない〇 《４》　　発明の目的 本５＆嘴は、上述の欠点に鑑み、パリティ検査手段自体
の故障を検出すると共にメモリから読み出された情報の
バリティとその読み出しアＦＬ／Ｘの関連性を確詔する
ことにより、読み出し情報の信頼性を向上させることを
目的とするものである。Furthermore, since the parity check itself has no relation to the read address, even if the parity is correct, there is no guarantee that it is being read from the address of the address. In view of this, the purpose of this invention is to improve the reliability of read information by detecting failures in the parity checking means itself and ascertaining the relevance of the parity of information read from memory and its read address FL/X. That is.

（５）発明の構成 かかる目的は１読み出し情報のバリティ検査手段を具備
したメモリ装置に於いて、読み出しアドレスの少なくと
も１ビットの状態に応じて該読み出し情報のバリティ検
査を偶数パリティ検査と奇数バリティ検査とに切り換え
る様にしたことを特徽とする誤り検出方式によって達成
される。(5) Structure of the Invention The object of the present invention is to provide a memory device equipped with a parity check means for read information, which performs an even parity check and an odd parity check in accordance with the state of at least one bit of a read address. This is achieved by an error detection method that is characterized by switching between.

（６）発明の実施例 以下図面を用いて本発明を詳細に説明する。(6) Examples of the invention The present invention will be explained in detail below using the drawings.

第２図は本発明の一実施例である。FIG. 2 shows an embodiment of the present invention.

図中、８ＥＬＦｉ切換回路、ＥＸは排他的論理和ゲート
、Ｒ８はセット・リセット回路であり第１図と同一番号
は同一部位を示す。尚、パリティ検査回路ＰＣは奇数パ
リティの時に１ｌ”レベルのエラー信号ＥＯを出力する
ものとする。In the figure, EX is an exclusive OR gate, R8 is a set/reset circuit, and the same numbers as in FIG. 1 indicate the same parts. It is assumed that the parity check circuit PC outputs an error signal EO of 1l'' level when the parity is an odd number.

本発明は、アドレスレジスタ▲凡の読み出しアドレスの
少なくとも１ビ，トの状１ｉＫ応じてバリティ検査の奇
偶を切換える様にしたものである。従２てメモリＭには
、それぞれのアドレス空間のパリティ検査の奇偶に対応
したバリティビットが付加された情報が記憶されている
。In the present invention, the parity check is switched between odd and even depending on the state of at least one bit of the read address of the address register. Therefore, the memory M stores information to which parity bits corresponding to the parity check of each address space are added.

本実施例に於いては、第２図に示す如く、アドレスレジ
スタの読み出しアドレスＡ　４　，，Ａ　Ｉの８ビ，ト
の状ＩＮＫ応じてパリティ検査が切換えられ、切換回路
ＳＥＬからは次表の関係で出力が発生する。In this embodiment, as shown in FIG. 2, the parity check is switched according to the 8-bit state INK of the read address A 4 , , A I of the address register, and the following table is used from the switching circuit SEL. The relationship produces output.

例えば読み出しアドレスのＡ●，▲１，▲鵞が＠Ｑｌ，
Ｉｌｌ，ＩＱ＠　であるアドレス空間では、偶数バリテ
ィ検査が行われ、切換回路は−ｌ―レベルの信号を出力
しており、一方そのアドレス空間の統み出情報のパリテ
ィが偶数であればパリティ検査回路ＰＣの出力は１１１
レベルであるので、排他的論理和ゲー｝ＥＸの出力はＩ
Ｑ１レベルとなりエラー信号ＥＯは出力されない。For example, read address A●, ▲1, ▲ goose is @Ql,
In the address space Ill, IQ@, an even parity check is performed, and the switching circuit outputs a -l-level signal.On the other hand, if the parity of the output information of the address space is even, the parity check is performed. The output of the circuit PC is 111
level, so the output of the exclusive OR game }EX is I
It becomes Q1 level and error signal EO is not output.

endpage:2 また偶数パリティであるべきところが奇数バリティであ
った場合には排他的論理和ゲー｝ＥＸの入力はＩＱＩ，
Ｉｌ＠となるのでその出力はｅ１ｓレベルとなり、セッ
ト・リセット回路Ｒ８がセットされてエラー信号ＥＯが
Ｉｌｌレベルとなる。endpage:2 Also, if the parity is odd when it should be even parity, the input of the exclusive OR game is IQI,
Since the signal becomes Il@, its output becomes e1s level, the set/reset circuit R8 is set, and the error signal EO becomes Ill level.

またパリティ検査回路ＰＣ自体が故障してその出力がＩ
Ｑ１レベルに固定されてしまったとしても、偶数パリテ
ィ検査を行なうアドレス空間の情報を読み出した時には
切換回路ＳＥＬの出力が１１１レベルとなるので排他的
論理和ゲー｝ＥＸの出力がｓ１ａとなってエラー信号Ｅ
Ｏが出力される。一方、パリティ検査回路ＰＣ自体の出
力がｌ１１レベルに固定されてＬまクた場合にも同様に
して奇数パリティ検査を行なうアドレス空間の情報の読
み出し時にエラー信号ＥＯが出力される。　　． 更に本実施例に於いては、読み出しアドレスと実際に読
み出された情報のメモリＭ中の領域が一致してーない場
合Ｋも、そのアドレス空間κ対応したパリティ検査の奇
偶と、読み出し情報のパリティの奇偶が一致せずエラー
信号ＥＯが出力されるので、所望のアドレス領域から情
報が読み出されているか否かも確認す．ることかできる
。Also, the parity check circuit PC itself has failed and its output is I
Even if it is fixed at the Q1 level, when the information of the address space for which even parity check is to be performed is read, the output of the switching circuit SEL will be at the 111 level, so the output of the exclusive OR gate EX will be s1a, causing an error. Signal E
O is output. On the other hand, even if the output of the parity check circuit PC itself is fixed at the l11 level and goes low, the error signal EO is similarly output when reading information in the address space where the odd parity check is performed. ．． Furthermore, in this embodiment, even if the read address and the area in the memory M of the actually read information do not match, the parity check corresponding to the address space κ and the read information Since the parities do not match even and odd and an error signal EO is output, check whether the information is being read from the desired address area. I can do that.

（７）発明の効果 以上説明した様に、本発明によれば、バリティ検査手段
自体の故障を検出することが可能とな９、更に読み出し
アドレスと読み出し情報の関連性もチェックされるため
、読み出し情報の信頼性をより向上させることが可能で
ある。(7) Effects of the Invention As explained above, according to the present invention, it is possible to detect a failure in the parity checking means itself.9 Furthermore, since the relationship between the read address and the read information is checked, the read It is possible to further improve the reliability of information.

【図面の簡単な説明】[Brief explanation of the drawing]

ｌｌｈｌ図は従来のハＩＪティ検査方式を適用したメモ
リ装置のブロック図、！ｓ２図は本発明の一実施例であ
る。 Ｍ・・・メモリ、ＤＥＣ・・・アドレスデコーダ、ＩＪ
Ｒ・・・データレジスタ、ＡＲ・・・アドレスレジスタ
、ＰＣ・・・パリティ検査回路、▲Ｂ・・・アドレスバ
ス、ＤＢ・・・テータパス、ＫＯ・・・エラー信号、Ｓ
ＥＬ・・・切換回路、Ｒ・８・・・セットリセット回路
、 ＥＸ・・・排他的論理和ゲート〇 endpage:3The llhl diagram is a block diagram of a memory device to which the conventional high IJT inspection method is applied. Figure s2 is an embodiment of the present invention. M...Memory, DEC...Address decoder, IJ
R...Data register, AR...Address register, PC...Parity check circuit, ▲B...Address bus, DB...Data path, KO...Error signal, S
EL...Switching circuit, R・8...Set reset circuit, EX...Exclusive OR gate〇endpage:3

Claims (1)

【特許請求の範囲】[Claims] 読み出し情報のバリティ検査手段を具備したメモリ装置
に於いて、読み出しアドレスの少なくとも１ビットの状
態に応じて該読み出し情報のパリティ検査を偶数パリテ
ィ検査と奇数パリティ検査とに切り換える様ｋしたこと
を特徴とする誤り検出方式。A memory device equipped with a parity check means for read information, characterized in that the parity check for the read information is switched between an even parity check and an odd parity check depending on the state of at least one bit of a read address. error detection method.
JP57052058A 1982-03-30 1982-03-30 Error detection system Pending JPS58169253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052058A JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052058A JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Publications (1)

Publication Number Publication Date
JPS58169253A true JPS58169253A (en) 1983-10-05

Family

ID=12904208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052058A Pending JPS58169253A (en) 1982-03-30 1982-03-30 Error detection system

Country Status (1)

Country Link
JP (1) JPS58169253A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473722B1 (en) 1997-12-18 2002-10-29 Nec Corporation Compact fault detecting system capable of detecting fault without omission

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473722B1 (en) 1997-12-18 2002-10-29 Nec Corporation Compact fault detecting system capable of detecting fault without omission

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