JPH06161804A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the burden of a software by preventing the contents of a RAM from being destroyed when performing the test of fault processing. CONSTITUTION:When any fault such as a parity error is generated, the generation of the fault is detected by a fault detecting circuit 2, and the generating part and cause of the fault are remained in a diagnostic register 3 readable/ writable from the software. Interruption is generated by setting a bit showing the fault generating part and cause in the diagnostic register 3 to '1'. Thus, since the interruption can be generated only by turning the bit showing the fault generating part and cause in the diagnostic register to '1' even without reloading the contents of the RAM, the burden of the software can be lightened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a failure detection and failure reporting method in the information processing apparatus.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional method in this method. When the failure detection circuit 2 detects the occurrence of a failure, the failure detection circuit 2 causes the instruction unit 4 to
At the same time as reporting that a failure has occurred, the location and cause of the failure are written in the diagnostic register 3.

In this method, when testing a software fault handling routine, for example, when testing a fault called a cache parity error, data that causes a parity error is written in the cache data in advance and that data is accessed. There was a method of causing a failure by doing so.

The test of the fault handling routine by this method is performed in the following procedure. First, data that causes a parity error is written to a certain address in the cache 5 by a cache write command. Then, the cache data is read from the same address. The read data is judged to be a parity error by the parity checker 6, that is, the failure detection circuit 2 detects a failure called a cache parity error. When the fault detection circuit 2 reports this to the instruction unit 4, the instruction unit 4 causes a fault interrupt, so that the fault handling test can be performed.

[0005]

In this prior art, the contents of the RAM such as the cache or TLB are destroyed when the failure handling routine is tested. Therefore, it is necessary to write a program in consideration that some of these contents will be destroyed. For example, if an address in the instruction cache is filled with data that causes a parity error, software must avoid accessing ordinary addresses at this address. Therefore, the software must be aware of the structure of the cache, such as which part of the instruction address is used as the index of the cache, so that the RAM failure does not affect other operations of the test program. The burden was heavy.

[0006]

According to the present invention, a bit indicating a fault occurrence site and a fault factor in a diagnostic register has a fault reporting function. By setting this bit to "1", You can make it appear to be faulty and generate an interrupt even if it is not.

[0007]

By using the method of the present invention, the failure handling routine can be tested without destroying the contents of the RAM. That is, in order to test the failure handling routine, even if the data causing the parity error is written in the cache data as in the conventional example and the failure is not caused by accessing the cache data, the failure location and cause of the diagnostic register It suffices to set the bit indicating "1" to "1", and the load on the software can be reduced.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 3 is an overall system configuration diagram of the present invention. The entire figure is built in one chip. In this figure, the instruction unit 101 analyzes and executes the instruction read from the instruction cache 106 through the path 201. The memory control unit 102 has an instruction cache / T
It controls built-in RAM such as LB 106 and data cache / TLB 107. The integer arithmetic unit 103 and the floating point arithmetic unit 104 respectively include a general-purpose register 10
8. The floating point register 109 is referenced to perform the operation.

When a fault occurs in this system, all the fault information is collected in the diagnostic register 110. Specifically, the information on the failure that has occurred in the built-in RAM is once collected in the memory control unit 102, and is collectively sent to the diagnostic register 110 here. Fault information generated in the RAM outside the chip is sent through the bus interface unit 105. Fault information generated in other units is directly sent to the diagnostic register 110. The diagnostic register 110 uses the RAM 30 as a signal to indicate failure information generated / detected in the RAM, bus, arithmetic unit, or the like.
1 to 305 receive and store, and report occurrence of failure to instruction unit. In addition, this diagnostic register 110 has a path 2
02, data can be exchanged with the general-purpose register 108, so that the value can be freely set by software.

FIG. 1 shows a block diagram of an embodiment of the present invention. Normally, when a failure occurs, the failure detection circuit 2 detects that a failure has occurred. The fault detection circuit 2 is
The failure occurrence part and factor are set in the diagnostic register 3 by the failure occurrence part and factor write signal 12.
For example, when a parity error occurs in the cache, the bit in the diagnostic register 3 indicating that the parity error has occurred in the cache is set to "1". Part,
When the factor is set, the fault detection signal 13 reports the occurrence of a fault to the instruction unit 4, and an interrupt occurs.

When testing fault handling, software executes a diagnostic register write instruction. When the diagnostic register write command is executed, the contents of the general-purpose register 1 are written to the diagnostic register 3 by the write signal 11 by software. The specific example is shown below.

FIG. 4 shows an example of the configuration of bits in the diagnostic register that indicate the location of failure and the cause. The diagnostic register is composed of 4 bytes and 32 bits, and the failure occurrence portion is stored in the 0th byte and the 1st byte of the register, and the failure occurrence factor is stored in the 2nd and 3rd bytes. In this configuration example,
When testing a failure that a parity error has occurred in the internal instruction cache, set the general-purpose register to "2000
After setting 4000 "(0 byte, 2nd bit, 2nd byte, 1st bit is" 1 "), the diagnostic register write instruction is executed.
When the diagnostic register write command is executed after giving a value so that the bit indicating the fault occurrence site and the fault factor in the diagnostic register 3 to be tested are set to "1", the fault occurrence site And the bit indicating the failure factor is set to "1". As a result, similarly to the case where the failure actually occurs, the failure detection signal 13 reports the occurrence of the failure (even if the failure does not actually occur) to the instruction unit 4 and causes an interrupt due to the failure. it can.

However, if a fault interrupt is generated during execution of the diagnostic register write instruction, the diagnostic register write instruction is re-executed after the interrupt processing is completed, so that an interrupt occurs again and an infinite loop occurs. Therefore, when the diagnostic register write instruction is being executed (at this time, the signal 14 for selecting the write by software is "1"), the failure part and the factor are set in the diagnostic register 3. However, the failure report to the instruction unit 4 is suppressed by the AND gate 7. The fault is reported after the signal 14 for selecting writing by software becomes "0" after the completion of the diagnostic register write command.

[0015]

As described above, according to the present invention, a failure report is made according to the status of a failure occurrence site in the diagnostic register and the status of the bit (for example, the status of the bit indicating that a parity error has occurred in the cache). In order to do so, the failure processing can be tested without increasing the amount of hardware and the contents of the cache, etc. can be tested by simply setting the bit indicating the failure occurrence part and factor to "1". Can reduce the burden.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 shows an overall configuration diagram of a system.

FIG. 4 shows an example of bit allocation of a failure occurrence site and a cause in a diagnostic register.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... General-purpose register, 2 ... Fault detection circuit, 3 ... Diagnostic register, 4 ... Instruction unit, 5 ... Cache, 6 ... Parity checker, 7 ... AND gate for suppressing fault report, 11 ... Software write signal, 12 ... Fault part and factor write signal, 13 ... Fault detection signal, 14 ... Signal for selecting writing by software, 101 ... Instruction unit, 102 ... Memory control unit, 103 ... Integer arithmetic unit, 104 ... Floating point arithmetic unit, 105 ... Bus Interface unit, 106 ... Instruction cache / TLB, 107 ... Data cache / TLB, 108 ... General-purpose register, 109 ... Floating point register, 110 ... Diagnostic register.

Claims (1)

[Claims] 1. An information processing apparatus comprising means for detecting the occurrence of a failure such as a RAM parity error and generating an interrupt and at the same time leaving a history of the failure occurrence site and failure factor. , A diagnostic register that can be read and written clearly by software, a means for setting a bit in the diagnostic register to "1" when a failure occurs, and the bit indicates a failure occurrence site and a failure factor and is set to "1". An information processing device, characterized in that it has a means for generating an interrupt.