JPH0481953A - Memory device - Google Patents

Abstract

PURPOSE:To improve the parity check of the memory device by holding an address in which an error is generated and a system of a memory at the time when a memory parity error is generated. CONSTITUTION:When a memory parity error is generated, an error bit is set and inputted to an interruption generating part 3. In the interruption generating part 3, it is held and an interruption is informed to a central processor 1, and also, an address in which an error is generated is held by an error generation address holding part 2, and in an error generation memory system holding part 4, a bit corresponding to the system which becomes effective at present is turned on in order to show in which system an error is generated. The bit which is turned on once is not turned off until it is decided that a memory function is normal by the central processor 1. In such a way, the system stop caused by generation of the memory parity error is reduced, and reliability of the whole system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory devices, and more particularly to improvements in parity checking of memory devices.

[Conventional technology]

Conventionally, a parity check in a memory device only involves notifying the central processing unit (CPU) of the occurrence of an error through an interrupt. Therefore, the CPU
According to a predetermined interrupt vector, the interrupt program branches to the first address where it is stored and performs some processing, but it is not possible to know the address where the error occurred. Furthermore, error correction using ECC is a method that is effective only in units of CPU accesses, and cannot cope with failures throughout the memory.

[Problem to be solved by the invention]

The above-mentioned conventional parity check function alone does not necessarily accurately determine the address where the error has occurred, and has the disadvantage that the system must be stopped unavoidably.

[Means to solve the problem]

The memory device of the present invention has n systems (n≧2) of memory that are controlled so that data is simultaneously written during writing and only one selected system is valid during reading, and an error occurs when a memory barrier error occurs. The error occurrence address holding section holds the address where the error occurred, and the error occurrence memory system holding section holds the memory system where the error occurred when the memory barrier error occurred.

The memory device of the present invention includes a memory of n systems (n≧2) that is controlled so that data is written simultaneously during writing and only one selected system is valid during reading, and a memory that prevents errors when a memory barrier occurs. It includes an error occurrence address holding section that holds the address where the error occurred and an error occurrence memory holding system section that holds the memory system where the error occurred when the memory barrier error occurred. With respect to the address held in the holding unit, reading of memory systems other than the memory system held in the error occurrence memory system holding unit is enabled, and the data read from the memory system of the above system is written to the memory of the n system. It is characterized by doing the following.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a central processing unit; 2 is a memory barrier error occurrence address holding unit; 3 is an interrupt generation unit that adjusts interrupt generation and error occurrence address holding timing; 4 is an error occurrence memory system identification signal holding unit; 5 is a write buffer; 6
is the 1st system read buffer, 7 is the 2nd system read buffer,
8 is an n-system read buffer, 9 is an access memory selection section, 10 is a 1-system parity detection/addition section, 11 is a 2-system parity detection/addition section, 12 is an n-system parity detection/addition section, 1
3 is 1-system memory, 14 is 1-system parity pit memory,
15 is a 2-system memory, 16 is a 2-system parity bit memory, 17 is an n-system memory, and 18 is an n-system parity bit memory. (n≧2).

In the figure, MRC (MRCI, MRC2,...MRCn)
, MWC1■OR, and IOW are command signals, which are a memory read control signal, a memory write control signal, and an I10 read control signal, respectively.

I10 write control signal. (MRCI.

MRC2, ---MRCn are memory read control signals for the 1st system, 2nd system, . . . n system) Next, an outline of the operation of this embodiment will be described.

The data output from the central processing unit 1 during writing is
Memories 13 and 15 respectively via write buffer 5
．． 17 is written. At this time, parity detection/addition section 1
0.11.12, parity bits for the 1st system, 2nd system, . . . n system are generated and written into the parity bit memories 14, 16.18. When reading, I1
The data in the system of memory (only one system out of n systems) selected based on the contents written in the access memory selection unit 9 by the 0 instruction becomes valid as read data.

When the 1st system is valid, data read from the 1st system memory 13 is taken into the central processing unit 1 via the 1st system readout buffer 6. At this time, the 1st system parity detection/addition section 1
0, the parity is detected along with the parity bit read from the 1st system parity bit memory 14, and when there is no error, the error bit does not go up, but when an error occurs, an error pit goes up and the interrupt generation unit 3 The input 0 interrupt generation unit 3 holds this and notifies the central processing unit 1 of the interrupt, and the error occurrence address holding unit 2 holds the address where the error occurred.
In the error occurrence memory system holding unit 4, turn on the bit corresponding to the system that is currently enabled to indicate in which system the error has occurred (only the parity error of the system that is enabled is enabled, interrupt generation unit 3 adjusts the timing).

Once turned ON, the bit is not turned OFF until the central processing unit 1 determines that the memory function is normal.

Even when the n-system is valid, the n-system circuit operates in the same manner as above.

When a parity error occurs during reading, an interrupt is generated in the central processing unit 1, and according to an interrupt vector specified in advance, the process branches to the start address of the interrupt processing routine when a memory barrier error occurs, and is executed. During this process, by referring to the error occurrence address holding unit 2, you can know the physical address where the parity error has occurred, and by referring to the error occurrence memory system holding unit 4, you can know which system of memory is currently normal memory. You can tell if it's a strain. Thereafter, the access memory selection unit 9 selects one of the remaining normal memory systems according to the contents of the error memory system holding unit 4.
It executes the I10 write command to read out the data at the physical address referenced by the error occurrence address holding unit 2, and at the same time writes that data to that physical address in the memories of all systems. By doing this, the data of the system where an accidental error has occurred is also corrected, allowing continuous operation of the system using the normal memory system.

In addition, if the memory is returned to the system where the error occurred and the same address is read out and no error occurs, this is treated as an accidental event and the memory system holding unit 4 where the error occurred
It is also possible to turn off the corresponding bit in the memory system and consider the memory system that is considered to be defective to be normal.

However, it is necessary to avoid system deadlock in the event that a memory barrier error occurs and a memory barrier error occurs in the interrupt processing routine.

〔Effect of the invention〕

According to the present invention, it is possible to reduce system stoppage due to the occurrence of a memory barrier error, and it is also possible to improve the reliability of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Error occurrence address holding unit, 3...Interrupt generation unit, 4...Error occurrence memory system holding unit, 5...Write buffer, 6...
1 system read buffer, 7...2 system read buffer, 8...n system read buffer, 9...access memory selection unit, 10...1 system parity detection/addition circuit, 11...・2 system parity detection/additional circuit, 12...
n-system parity detection/addition circuit, 13...1-system memory,
14...1 series parity bit memory, 15...2
System memory, 16...2 system parity bit memory, 1
7...n-series memory, 18...n-series parity bit memory.

Claims (1)

[Claims] 1. A memory of n systems (n≧2) that is controlled so that data is simultaneously written during writing and only one selected system is valid during reading, and a memory parity error occurs. The present invention is characterized in that it includes an error occurrence address holding section that holds an address where an error has occurred at the time of occurrence, and an error occurrence memory system holding section that holds the memory system where the error has occurred when a memory parity error occurs. memory device. 2.N systems of memory (n≧2) that are controlled so that they are simultaneously written when writing and only one selected system is valid when reading, and the address where an error occurred when a memory barrier occurred. and an error occurrence memory retention system section that retains the memory system in which the error occurred when a memory parity error occurs, and an error occurrence address retention section that retains the error occurrence address retention section when a memory parity error occurs. Enabling reading of memory systems other than the memory system held in the error occurrence memory system holding unit for the held address, and writing data read from the n system memories to the n system memories. A memory device characterized by: