JPH0778747B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention 【Overview】

A data processing device that corrects memory data by a microinstruction when a 1-bit error occurs in a read access of a memory, with an object of relieving a 1-bit error as a soft error without reducing performance.
When the ECC circuit detects a 1-bit error, the error occurrence address is held in the error address register, and in response to an interrupt from the ECC circuit, the processor executes a microinstruction to access a specific address in another external register space different from the memory access space. By doing so, the error address of the error address register is set in the physical address register, and data reading, correction of the read data, and writing of the corrected data are performed by one access.

[Industrial applications]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device which corrects memory data by a microinstruction when a 1-bit error occurs in a memory read access. It is known that in a large-capacity semiconductor memory, an error occurs in which information stored in a memory cell is bit-inverted, and once inverted, the bit "0" or "1" remains
The error that is fixed to is called a hard error, and the error that corrects even if it is reversed and correct information is called a soft error. In general, the frequency of soft errors is 10-100 of hard errors.
It is known that this is about twice as high. Therefore, in a data processing device that uses a memory device that uses a large number of large capacity semiconductor memories, a 1-bit error that occurs during reading is corrected and a 2-bit error is detected. It is usually equipped with an ECC circuit.

[Prior art]

By the way, early 64Kbit DRAM with high soft error rate
In the era when was used, there was a high probability that a 1-bit error due to a soft error would occur in another bit of the same address and result in a 2-bit error, making it uncorrectable when read by the CPU. A system that performs patrol of memory is known. This memory patrol is a function to perform 1-bit error correction and rewrite of corrected data by read / ECC for all addresses while periodically changing the address for the memory. This is performed by hardware and by firmware. There are cases. In the case of memory patrol performed by hardware, a patrol address register and patrol cycle counter are provided, and when the patrol cycle comes, the memory address set in the patrol address register is read, corrected, and rewritten by hardware, and then patroled. The address register is incremented and the same processing is performed in the next patrol cycle. Therefore, in the case of hardware, in addition to the patrol address register and the patrol cycle counter, an increment circuit and a read / correction / write circuit dedicated to patrol are required. On the other hand, in the case of memory patrol performed by firmware, when the patrol cycle comes, the firmware is notified by an interrupt, etc., and the firmware sets the patrol address in the physical address register, reads the memory, and executes the EC.
The C circuit corrects the 1-bit error and rewrites. The patrol address is stored in a predetermined area of the control memory, read only when patrol is performed and set in the physical address register, and after patrol access, the patrol address is incremented by the firmware and stored in the original area. This firmware method requires less hardware configuration than the hardware method, but because the firmware interrupts the processing up to that point and performs a patrol operation, the performance of the data processing device is reduced. To do. Of course, even with the hardware method, normal memory access is kept waiting during the memory access operation during patrol,
Performance is down, though not as much as the firmware method. In contrast to the conventional semiconductor memory that requires such memory patrol, in recent years, an element in which some measure against soft error has been implemented by the memory itself appears, and the occurrence rate of soft error is not so high. The probability of being uncorrectable due to a double-bit error becomes extremely low. As a result, a system that does not perform a memory patrol operation that leads to performance degradation has appeared.

[Problems to be Solved by the Invention]

However, in a system that does not perform a memory patrol operation, although there is a low probability that a system error will occur due to a 2-bit error due to overlapping soft errors, the area in which a 1-bit error has occurred once is read unless that area is rewritten. One bit error every time. In the case of a 1-bit error, the clock is usually stretched in anticipation of the data correction time by the ECC circuit, the time for data to arrive at the processor is delayed, and the performance is reduced accordingly. Further, the 1-bit error is not directly connected to the system and the processing is continued, but when the 1-bit error occurs, the logging processing for storing the error information is performed.
Therefore, if the same area is frequently read without correcting the 1-bit error, the logging process may be performed each time and the logging area may be insufficient. Also, if the number of 1-bit error occurrences exceeds a certain number of times, the possibility of a hardware error increases, so error information may be output as a message on the screen of the console, etc. I will call a system engineer to replace the memory,
The error may be accumulated due to a soft error, and the error will not be reproduced even if the memory in which the error occurred is tested by the test department. In other words, the wasteful work of exchanging the memory that is not a hard error is purposely performed, which causes a loss of maintenance and inspection work and costs, and annoy the user. The present invention has been made in view of such conventional problems, and an object thereof is to provide a data processing device capable of relieving a 1-bit error as a soft error without degrading the performance.

[Means for Solving the Problems]

FIG. 1 is an explanatory view of the principle of the present invention. In FIG. 1, the data processing device 100 sets the address of the memory device 10 in the physical address register 20 to read or write. At the time of reading, the ECC circuit 12 detects a 1-bit error included in the data read from the memory device 10.
Detect with and correct. According to the present invention, when the ECC circuit 12 detects a 1-bit error when the memory device 10 is read, the memory address of the physical register 20 at that time is held in the error address register 14 as an error occurrence address. The processor as the control means 18 modifies and uses the function of the already prepared test and set instruction as a read / correction / write instruction for a 1-bit error. The test-and-set instruction is a microinstruction executed by an access designating a specific address in which an external register does not exist among addresses designating an external register space. When accessing the test and set instruction, the memory device is addressed by the physical register 20.
10 is read, a specific bit of read data (the most significant bit is set to 1) is modified, and the process of writing the modified data to the original address is executed by one access. Therefore, the present invention suppresses the specific bit correction function of the test-and-set instruction when receiving the detection notification of the 1-bit error from the ECC circuit 12, and thereby the read / correction / write instruction of the 1-bit error is suppressed. Read from the error occurrence address of the memory device 10 set in the physical address register 20, the detection and correction of the 1-bit error of the read data by the ECC circuit 12, and the writing of the corrected data to the memory device 10 to 1 Execute with one access. One access means locking the common bus so that the read data is not taken into the processor and the area read by another processor or DMA device is not rewritten during "read / correct / write". Means access.

[Action]

When the processor performs read access to the memory and, for example, a 1-bit error occurs, the error occurrence address is stored in the error address register, the ECC circuit causes an interrupt to the processor, and the processor triggers the interrupt to read the error address register. To the physical address register and execute read / correction / write instructions. This read / correction / write instruction can be read from the address in which a 1-bit error occurs in the memory device by simply modifying the 1-bit correction function of the already prepared test-and-set instruction. , 1-bit error detection and correction by read data ECC circuit,
Further, it is possible to write the corrected data to the memory device with one access. As a result, if there is a soft error, the data returns to the normal state, and a 1-bit error will not occur in the subsequent read access. Of course, in the case of a hard error, the data does not return to the normal state, and a 1-bit error occurs in the read access again, but this makes it possible to relieve a soft error, which is much more frequent than a hard error, without lowering the performance. In addition, the 1-bit error read / correction / write instruction is a modification of the existing test-and-set instruction and is executed.
Read and write are performed as a set instruction, and read / write
There is a merit that it is not necessary to newly control the bus as a correction / write instruction. Also existing test and
Even if the set instruction is changed to a read / correction / write instruction, a simple addition of hardware for suppressing the 1-bit correction function is sufficient.

【Example】

FIG. 2 is an explanatory view showing an embodiment of the present invention. In FIG. 2, reference numeral 100 denotes a data processing device, and the data processing device 100 includes a plurality of memory devices (semiconductor memories) 10.
, a, 10b, ... Are connected by a memory data bus and a memory address bus. The data processing device 100 is provided with a microprocessor 18a as a control means and a physical address register 20 in which a physical address for making a read access to the memory device 10a is set. For the physical address register 20, a microprocessor is provided. If the physical address for read access is directly set from 18a or in the virtual memory system, the address data converted from the virtual address to the physical address by the address conversion circuit 22 is set. Further, the data processing device 100 is provided with an ECC circuit 12 for detecting and correcting a 1-bit error of read data read from the memory device 10a or 10b by read access. Further, the microprocessor 18a is provided with an external register 16a having another external address space different from the memory access. Although the configuration of such a data processing device 100 is the same as the conventional one, in addition to this, in the present invention, an error address register 14 is newly provided and an EC is provided by a read access.
When the C circuit 12 detects a 1-bit error, the error occurrence address set in the physical address register 20 in response to the error detection output of the ECC circuit 12 can be stored in the error address register 14. In addition to such an error address register 14, the microprocessor 18a
When the ECC circuit 12 receives an interrupt based on the detection output of a 1-bit error, the error address of the error address register 14 is set in the physical address register 20 to read the data, correct the read data, and write the corrected data. As a microinstruction to be performed with one access,
"Read / correct / write instructions" are prepared. "Read / correction / write instruction" as this micro instruction
Is an instruction to access a specific address of the external register 16a that creates another external address space different from the memory access space. For example, an external register address that does not exist is used as the specific address of the external register 16a. By executing an instruction to write access to the register address, the operation of "read / correction / write instruction" can be performed by one access. Next, the processing operation when a 1-bit error occurs in the read access in the embodiment of FIG. 2 will be described. Now, it is assumed that the microprocessor 18a of the data processing device 100 sets a read address in the physical address register 20 directly or via the address conversion circuit 22 to access the memory device 10a. In response to this read access, the memory device 10a receives the data processing circuit 100 through the memory data bus.
To the microprocessor 18a via the data bus via the ECC circuit 12. At this time, if the ECC circuit 12 detects a 1-bit error that has occurred as a soft error, the ECC circuit 12
In response to the error detection output, the read address set in the physical address register 20 is held in the error address register 14 as the error occurrence address. On the other hand, when the ECC circuit 12 detects a 1-bit error, it notifies the microprocessor 18a of the error detection. This error notification triggers the processor 18a to read, correct,
Execute a write command. That is, the microprocessor 18
a performs a write access to a specific register address of the external register 16a, for example, an external register address that does not exist, and the error occurrence address held in the error address register 14 is set in the physical address register 20 in response to this write access. Data is read from the error occurrence address of the memory device 10a, the read data in which the 1-bit error has occurred is fetched into the ECC circuit 12 and is corrected, and after correction, the correction data can be written to the same address by one access. To do. Therefore, since it is a soft error, the memory device 10a
The error occurrence data of No. 1 is restored to the normal state, and the 1-bit error does not occur in the subsequent read access of the same address. In the embodiment of FIG. 2, the memory devices 10a, 10b ,.
The other data processing device 100a is connected to the data bus and the address bus of, and the other data processing device 100a is provided with the error address register 14 as well as the data processing device 100. Similarly, by providing a "read / correction / write instruction", when a 1-bit error due to a soft error occurs, it is possible to restore the memory data to a normal state by executing a micro instruction by an interrupt. FIG. 3 shows a "test and set instruction" provided as a micro instruction by the data processing device 100 shown in FIG.
A specific embodiment in which the "read / correction / write instruction" is executed when a 1-bit error is detected by using In FIG. 3, the microprocessor 18a is provided with an external register as shown in FIG. 2 separately from the memory access space.
The external register 16a has an external register space, and external register addresses are allocated to the external registers 16a, respectively, and data of the external register 16a can be read or written by an MV instruction (MOVE instruction). In addition to such an external register space access function, the microprocessor 18a normally performs one operation when an external register address where an external register does not exist is specified, but a special function is provided by specifying this nonexistent external register address. Can be held. In the embodiment shown in FIG. 3, the external register address can have from "X80" to "XFF".
There are external registers from "X9F" to "X9F", but "XA0"
There are no external registers from to "XFF". When the microprocessor 18a performs a read access by designating a register address "XA0" that does not exist as an external register address, the address "XA0" is decoded by the external decoder circuit 24 and a "test and set instruction" is executed. be able to. Here, the "test and set instruction" is to read data in a designated area of the memory device and to read a specific 1 bit of the read data, that is, the most significant bit in this embodiment is "1". It is a function to write to the original area as it is. Of course, if there is a 1-bit error in the read data, the most significant bit is set to "1" and written after correction. The area to be the target of the "test and set instruction" is specified by setting an address in the physical address register in advance by the processor 18a. Explaining the configuration of the data processing device of FIG. 3 provided with such a "test and set instruction", the ECC circuit 12 is provided with a check bit generator 26 for adding a check bit to write data. On the other hand, in order to detect and correct a 1-bit error from the read data fetched from the memory data bus via the read data register 28 by the read access and detect a 2-bit error, the syndrome generator 30, the syndrome decoder 32, and A data modifier 34 is provided. On the other hand, a correction circuit for setting 1 to the most significant bit of the read data obtained via the data correction unit 34 of the ECC circuit 12 in order to execute the "test and set instruction".
38 is provided and a test and set instruction is given to the correction circuit 38 from the AND gate 40. AND gate 4
The decoded data obtained from the external decoder circuit 24 by inputting the address "XA0" of the external address register where the microprocessor 18a does not exist is input to one input of 0, and the other input of the AND gate 40 is a microprocessor. A write signal (indicating read at L level) from the processor 18a is input, and an inversion state of the write signal at L level allows the test and set instruction signal from the gate 40 to the correction circuit 38. It is possible to output. In order to realize the "read / correction / write instruction" according to the present invention, the "test and set instruction" composed of the correction circuit 38, the AND gate 40 and the decoder 24 is ANDed.
A gate 42 is provided, and the AND gate 42 receives the decoded output of the external register address "XA0" from the decoder 24 and also receives the write signal (H) from the microprocessor 18a.
Level). Therefore, the AND gate 42 corrects the correction circuit 38 when the microprocessor 18a performs a write access designating the external register address "XA0".
In response, an H level output for read / correction / write instruction is generated. The correction circuit 38, which has received the H level output of the read / correction / write instruction by the AND gate 42, does not perform the process of setting 1 to the most significant bit of the read data in the “test and set instruction”, and directly writes it. And the result is that the “read
"Correct / write instruction" can be realized. Incidentally, the microprocessors 18a, E in the embodiment of FIG.
The configuration other than the CC circuit 12 is the same as that of the embodiment shown in FIG. Next, the processing operation of the embodiment shown in FIG. 3 will be described. Read data register through memory data bus for read access of memory device by microprocessor 18a
When read data is stored in 28 and a 1-bit error is detected from the syndrome by the syndrome generator 30 and the syndrome decoder 32 provided in the ECC circuit 12,
The data is corrected by the data corrector 34, and the read data is taken into the microprocessor 18a via the correction circuit 38 and the transceiver 44. On the other hand, when the ECC circuit 12 detects a 1-bit error, the error occurrence address is held in the error address register 14 as shown in FIG.
When a receives an interrupt due to the error detection output from the ECC circuit 12, the microprocessor 18a executes the MV instruction for write access to the nonexistent external register address "XA0". That is, the microprocessor 18a uses the M
At the same time that the V instruction is output, the nonexistent external register address "XA0" is set, and in response to this, the external decoder 2
It produces an H level output on the signal lines for the four AND gates 40 and 42. At the same time, since it is a write access, the microprocessor 18a produces an H level output to the AND gates 40 and 42, and therefore the AND gate 40 is placed in the prohibition state, but the AND gate 42 is in the permitting state and the external decoder 24 The decoded signal passes through the AND gate 42 and gives the correction circuit 38 an H-level output which is a read / correction / write instruction. The correction circuit 38, which has received the instruction of the read / correction / write instruction, sets the error occurrence address stored in the error address register 14 in the physical address register 20 to read the memory device, and the read data is read by the ECC circuit 12
1-bit error is corrected when passing through the correction circuit 38
Then, the correction circuit 38 performs a write operation to write the corrected data to the original address as it is, whereby a "read / correction / write instruction" can be made by one access.
Is performed. As described above, in the embodiment of FIG. 3, since the hardware of the “test and set instruction” of the data processing device is effectively used, a 1-bit error is made by one access. The addition of hardware can be done by adding a very small amount of hardware. Of course, the realization of the "read / correction / write function" by the execution of the microinstruction when the 1-bit error is detected is not limited to the use of the "test and set instruction" of the data processing device, and the appropriate nonexistent The same can be realized by providing a special function using read or write access to the external register. [Effects of the Invention] As described above, according to the present invention, when a processor reads and accesses a memory and a 1-bit error occurs, a 1-bit correction function included in a test and set instruction that has already been prepared. By executing a read / correction write command that suppresses the 1-bit error of the memory device, the ECC circuit for the read data detects and corrects the 1-bit error, and the corrected data is transferred to the memory device. Writing can be done with a single access. This 1-bit error read / correction / write instruction is a modification of the existing test and set instruction and is executed. Therefore, read and write are performed as the original test and set instruction on the bus. There is no need to newly control the bus as a read / correction / write instruction.
Further, even if the existing test-and-set instruction is changed to a read-correction-write instruction, a simple addition of hardware for suppressing the 1-bit correction function is sufficient. As a result, by adding a small amount of hardware, it is possible to relieve the soft error by rewriting the data of the memory address that has generated the 1-bit error, and the performance of the memory is not reduced as in the case of the memory patrol. The reliability of can be improved.

[Brief description of drawings]

1 is an explanatory view of the principle of the present invention; FIG. 2 is an explanatory view showing an embodiment of the present invention; FIG. 3 is a "read-and-read function" utilizing a "test and set function" of a data processing device. It is explanatory drawing which showed the specific Example which implement | achieves a "correction / write function." In the figure, 10,10a, 10b: Memory device (semiconductor memory) 12: ECC circuit 14: Error register 16: External register space 16a: External register 18: Control means 18a: Microprocessor 20: Physical address register 22: Address conversion circuit (For virtual memory) 24: External decoder circuit 26: Check bit generator 28: Read data register 30: Syndrome generator 32: Syndrome decoder 34: Data corrector 38: Correction circuit 40, 42: AND gate 44: Transceiver

Claims (1)

[Claims] 1. A physical register (20) is set with an address of a memory device (10) for reading or writing, and at the time of reading, a 1-bit error included in data read from the memory device (10) is detected by an ECC circuit ( A data processing device that detects and corrects data in 12) includes an error address register (14) and a control means (18), and the error address register (14) includes the ECC circuit (1).
When the 1-bit error is detected by 2), the memory address of the physical register (20) is held as an error occurrence address, and the control means (18) actually selects the external register space among the addresses that specify the external register space. The memory device (10) is read by the address designation by the physical register (20) as a microinstruction executed by an access designating a specific address that does not exist, and a specific bit of the read data is modified to modify the modified data. Has a test-and-set instruction for writing to the original address, and when the test-and-set instruction is executed as a read instruction, the test-and-set instruction is performed by modifying a specific bit.
The ECC circuit (12) has a function to function as a set instruction and to change to a 1-bit error read / correction / write instruction by suppressing modification of a specific bit when executing as a write instruction. When the read / correction / write command is executed upon receipt of a bit error detection notification, read from the error occurrence address of the memory device (10) set in the physical address register (20), and read of the read data A data processing device, wherein detection and correction of a 1-bit error by an ECC circuit (12) and writing of corrected data to the memory device (10) are executed by one access.