JPS61290556A - Memory error recovering system - Google Patents

Abstract

PURPOSE:To prevent the generation of a two bits error by executing preferentially read-out/write operations with respect to an error address which has stored a patrol diagnosis to a semiconductor memory, and executing one bit error correction in an early stage. CONSTITUTION:For instance, when the data from an outside is written in a memory 4, and this data is being read out, a one bit error is detected by an ECC circuit 5. It is informed to an address register 101 and a memory 102 from the circuit 5, the register 101 is set to +1, a correction controlling circuit 103 sets it to '0' by subtracting '1', and the contents of the memory 102 are set to an address counter 2. By this address, the data of the memory 4 are read and the data which has been corrected by the circuit 5 are stored in a register 6. As this this operation, since the circuit 103 is executing a patrol diagnosis, a report from the circuit 45 is prevented. On the other hand, the register 6 rewrites the corrected data to the memory 4 through a priority circuit 7, and prepares a one bit error part for generation of the next on or two bit error by adding ECC to the normal data.

Description

[Detailed Description of the Invention] [Summary] This is a memory error recovery method that stores an error address when a 1-bit error is detected during data transfer in a semiconductor memory, and stores patrol and diagnostic information for the semiconductor memory. The read/write operation is performed preferentially on the error address in which the error occurs, and the 1-bit error is corrected at an early stage, thereby preventing the occurrence of 2-bit errors.

[Industrial application field]

The present invention relates to a memory error recovery method for quickly correcting 1-bit errors called soft errors that occur in semiconductor memories.

With the expansion of the scope of use of information processing devices and the rapid development of semiconductor technology, semiconductor memories have come to be used as storage devices in all kinds of information processing devices.

This semiconductor memory has one-bit errors called soft errors that are temporarily generated by noise caused by weak radiation that exists in nature, and currently there is no way to prevent these one-bit errors.

Therefore, one of the countermeasures is to use error correction codes (hereinafter referred to as E).
In addition, a system called a patrol diagnosis system is implemented in which 1-bit error is corrected by using CC (referred to as CC), and if there is a 1-bit error when reading data from a semiconductor memory at any time, rewriting is performed using corrected data to prevent 2-bit errors.

It is hoped that a more reliable method will be put into practical use as a countermeasure against 2-bit errors in semiconductor memories employing this method.

[Prior art and problems to be solved by the invention] FIG. 3 shows a block diagram illustrating a conventional example.

This shows a block diagram when writing/reading data to/from data memory 4. Address register 1 specifies the address for writing/reading data to/from memory 4, and memory 4 for patrol diagnosis. Address counter 2 specifies the address for writing/continuing data to the address register 1 and address counter 2 are selected, and especially if they are input at the same time, address register 1 is selected.
a priority selection circuit 3 that preferentially selects input from a data memory 4 made up of a plurality of semiconductor elements; and an ECC that corrects and detects bit errors in data read from the data memory 4 using an added ECC. The circuit 5, the data register 6 which stores the data output from the ECC circuit 5, the input of the data transferred from the outside and the data from the data register 6, that is, the data read by patrol diagnosis. If a bift error has occurred, select the input of data ■ which is normal by the ECC circuit 5,
A priority selection circuit 7 that preferentially selects data ■ especially when input at the same time, and data ■ selected by the priority selection circuit 7.
It is comprised of a data register 8 for storing the data register 8 or (■), and a BCC generating circuit 9 for generating an ECC to be added when the data register 8 is stored in the memory 4.

During data transfer with the outside, the address to be read/written in the memory 4 is set in the address register 1, and if it is a read, the data at the address specified in the address register 1 passes through the ECC circuit 5 and is transferred to the data register 6. Stored.

At this time, if a bit error is detected in the ECC circuit 5,
The bit error is reported to another circuit (not shown) and the data transfer is interrupted, or the data transfer is continued and the bit error is reported after the data transfer is completed.

On the other hand, address counter 2 is used except when transferring data to the outside.
The address of the memory 4 is started from the smallest number, ie, address "O", and is cyclically instructed up to the largest address.

Read the data in memory 4 using this address, and
It is temporarily stored in the data register 8 via the circuit 5 - data register 6 - priority selection circuit 7, and then stored in the address counter 2.
Write again to the address indicated by. At this time, the ECC output from the FCC generation circuit 9 is added and written.

The above patrol diagnosis is executed cyclically regardless of the 1-bit error detected during data transfer, so the next patrol diagnosis will be performed by specifying the address where the 1-bit error occurred and rewriting the 1-bit error. It takes time to correct the error, and there is a great risk that a 2-bit error will occur during this period and become uncorrectable.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

FIG. 1 shows the address register 1 address counter 2. Priority selection circuits 3, 7. Data memory 4. E
CC circuit5. It consists of a data register 6.8ECC generation circuit 9, and a 1-bit error processing unit 10 that stores the address at that time when a 1-bit error is detected during data transfer and sets the address counter 2 to that address. .

[Effect]

If a 1-bit error is detected during data transfer with the outside, the address at that time is memorized and the address counter is set to that address, and the next patrol diagnosis will process the address where the 1-bit error was detected as the top priority. By doing so, it becomes possible to prevent the occurrence of 2-bit errors as much as possible.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

The 1-bit error processing unit 10 of this embodiment shown in FIG. 2 counts the number of times a 1-bit error occurs. In addition, there is an address register 101 that specifies the address to access the memory 102, a memory 102 that stores the address of the memory 4 when a 1-bit error occurs, and a memory 102 that monitors the contents of the address register 101 to recognize the occurrence of a 1-bit error and correct it. and an error recognition and correction control circuit 103 that controls the error recognition and correction control circuit.

Next, the operation of this embodiment will be explained focusing on the operation of the 1-bit error processing section 10.

Data ■ transferred from an external source (not shown) is written to the data memory 4 under the direction of the address register l,
The written data ■ is transferred to the memory 4 as data ■ to be transferred to an external device (not shown) under the direction of the address register l.
Suppose that a 1-bit error is detected by the ECC circuit 5 while reading from the data.

At this time, the ECC circuit 5 notifies the address register 101 and the memory 102 that a 1-bit error has occurred. . At the same time, the address contents at that time are stored in the memory 102 via the priority selection circuit 3, and the address register 101 is
1”.

The error recognition correction control circuit 103 is the address register 10
1, and if the content is not "0", that is, "+1", the content of the address register 101 is r
-IJ and set to "0", and the contents of the memo 'month 02 are read and set in the read address counter 2. ' The data in the memory 4 is read according to the address set in the address counter 2, and the data corrected by the ECC circuit 5 is stored in the data register 6. At this time, a bit error is reported from the ECC circuit 5 to the address register 101 and the memory 102, but the error recognition correction control circuit 103
Since it is said that patrol diagnosis is in progress, the operation based on the report from the ECC circuit 5 is prevented.

On the other hand, the data register 6 temporarily stores the stored correction data in the data register 8 via the priority circuit 7 and rewrites it in the data memory 4, thereby correcting the 1-bit error detected during data transfer. Restore normal data. In addition, at this time, the EC generated from the ECCCC generation path to the path
C is added to restore the error and prepare for the next 1-bit error or 2-bit error.

[9th Effect of Invention] According to the present invention as described above, when an l-focus error is detected, the patrol diagnosis processes the address where the l-focus error is detected with the highest priority, thereby omitting the occurrence of a two-bit error. It has the effect of being able to prevent it from happening.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1.101 is an address register, 2 is an address counter, 3.7 is a priority selection circuit, 4 is a data memory, 5 is an ECC circuit, 6.8 is a data register, 9 is an ECC generation circuit, °lO is 1 Bit error processing section, 102 is a memory, 103 is an error recognition correction control circuit, Himaya 3 figure

Claims (1)

[Claims] The data memory (4) is constituted by a semiconductor memory element, and the data stored in the data register (8) is transferred to the data memory (4) by an error correction code (ECC) generating circuit (9).
At the same time, the data memory (4) is always read out at the address specified by the address counter (2) to check whether there is a 1-bit error, regardless of the data recording operation. In a storage device that performs diagnostics to detect and prevent the occurrence of 2-bit errors, the data memory (4) is patrolled sequentially starting from the lowest numbered address. a 1-bit error processing unit that stores the 1-bit error occurrence address detected by the error correction code (ECC) circuit (5) during the read/write operation of the data to be transferred ([2]), and stores the number of occurrences thereof; (10), when the number of 1-bit error occurrences stored in the 1-bit error processing unit (10) is other than zero, the 1-bit error stored in the 1-bit error processing unit (10) occurs; A memory error recovery method characterized in that the 1-bit error is recovered by reading data from the data memory (4) from an address, correcting it, and then rewriting it to the data memory (4).