JPS61123957A - Storage device - Google Patents

Abstract

PURPOSE:To reduce soft errors by detecting the errors after reading total address space of a storage circuit every prescribed times period required for a refresh cycle, correcting these errors to write them in the storage circuit and shifting to refresh operation. CONSTITUTION:After generating internal information through an address generating circuit 15 every period of integral times of refresh operation period, a normal reading is executed to a storage circuit 6 corresponding to the internal address. If there is no error, as a result of detecting the read data of this address by means of an error detecting/correcting circuit 8, normal refresh operation is executed in sequence. On the other hand, if one bit error is detected in the error detecting/correcting circuit 8, writing is executed after correcting the said bit, the corrected data is again written in the storage circuit of same address via a switch 2 and an error correction signal generating circuit 4, and then normal refresh operation is started. Thus it is possible to save the soft errors by above-mentioned sequential operations for total address space of the storage circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION 1.1 The present invention relates to a memory device, and more particularly to a memory device that uses a semiconductor dynamic memory element and is designed to relieve the occurrence of so-called soft errors caused by α rays in the memory element. .

As the density of semiconductor dynamic storage elements increases, α rays emitted from the case material of storage devices cause destruction of stored information, resulting in so-called soft errors.

As a remedy for such soft errors, conventional memory vt
In W, a 1-bit correction/2-bit error detection function is added, and when a 1-bit error is detected during an external read operation, the error bit is corrected and the data is transferred to the external device, and the 1-bit error is It is also designed to send a machine error detection signal. In this case, the external device issues an operation interrupt in response to this error detection signal, transfers the received read data to the storage device again as write data, and executes the write operation.

In such a method, an increase in interrupt control in external devices results in a decrease in throughput between the storage and the device.
Furthermore, storage devices have the disadvantage that if soft errors occur at addresses that have not been accessed and these occur at the same address, there is an increased chance of uncorrectable errors.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional devices described above, and its purpose is to detect errors by reading out the entire address space of a memory circuit at a cycle that is a predetermined multiple of the refresh operation cycle. If an error is detected, it is corrected and written to the memory circuit, and then the refresh operation is started. This shortens the processing time for repairing soft errors caused by alpha rays in the memory element, and provides efficient error relief. An object of the present invention is to provide a storage device that does the following.

Configuration of the Invention A storage device according to the invention includes a dynamic storage element,
an error correction code generating means for adding an error correction code to write data and writing it into a storage element; an error detection and correction means for detecting occurrence of a 1-bit error in read data from the storage element and correcting the error bit; A memory device comprising a refresh control means for controlling a refresh operation of the memory contents of the element, and a reading means for reading data from the memory element in response to a refresh interrupt request every predetermined times the refresh operation period. , and writing means for instructing to write the corrected data into the storage element only when the read data is detected and corrected by the error detection and correction means, and the refresh am means controls the operation of the reading means and the writing means. It is characterized in that it is configured to perform a refresh operation after the refresh operation is completed, and to release the refresh interrupt request after the refresh operation is completed.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, write data 1 from an external device (not shown) is manually operated by a data selection switch 2. In FIG. This switch 2
In addition, an output 9 of a 1-bit correction/2-bit error detection circuit 8 is supplied to the input, and this output 9 is also supplied to an external device as read data from the storage device. The data 3 selected by the switch 2 is added with an error correction code in the error correction code generation circuit 5, becomes write data 5, and is inputted to the storage circuit 6. The read data 7 from the storage circuit 6 is input to the error detection and correction circuit 8, where the error is detected and corrected and becomes the previous read data.

An address signal 10 from an external device is applied to one signal selection switch 11, and an address signal 16 generated from an internal address generation circuit 15 is applied to the other inputs. This internal address generation circuit 15 receives the refresh interrupt signal 14 from the refresh interrupt control circuit 13 and counts it up to a predetermined time.The internal address generating circuit 15 further counts the output 26 of the multiplier circuit 25.
It has several circuits, and its output becomes the address signal 16 for refresh. The refresh interrupt control circuit 13 has a timer circuit necessary for periodically performing a refresh operation, and this timer circuit generates a refresh interrupt request signal 14 periodically and sends it via the multiplier circuit 26. It is transferred to the internal address generation circuit 15 and an external device.

Address 10 from external device and internal address generation circuit 1
The address from 5 is the address signal selection switch 12.
is selectively selected and becomes the address of the memory circuit 6.

Reference numeral 21 denotes operation designation information and operation request signals transferred from an external device, which are supplied to the operation decoding control circuit 22, and from this operation Wi reading sub-control circuit 2, an operation request signal 23 and various operation designation signals 24 are sent, respectively. The refresh holding circuit 17 receives the operation request signal 23, the refresh interrupt request signal 14, and the refresh request signal 1.
If there is an operation request signal when there is no refresh request using the multiplied output 26 of 4 as input, control is performed according to the operation specification from the external device.On the other hand, if there is a refresh interrupt request when there is no operation request signal, the storage circuit A refresh operation υJIIl is performed for 6. Also, this circuit 17
If the refresh interrupt request signal and the operation request signal overlap for a certain period, the operation request signal is given priority and executed,
l1lI executes refresh operation after completion of the operation
It has the function of III.

The output 18 of the refresh waiting circuit 17 and various operation designation signals 24 are input to a timing signal generation circuit 19, which generates timing signals necessary for controlling each operation designation. One of these timing signals 20 is supplied to the memory circuit 6 and becomes a row address strobe, a column address strobe, and an interrupt timing signal.

In a memory device with such a configuration, the relief process for soft errors caused by alpha rays in semiconductor dynamic memory elements is to correctly restore the errors in information held in the memory cells, and therefore the entire address space of the memory circuit is allocated appropriately. If a read operation is performed periodically and a 1-bit error is detected as a result, the error in that bit may be corrected and then a write operation may be performed on the address again.

Therefore, internal address information is generated from the address generation circuit 15 every cycle that is an integral multiple of the refresh operation cycle, and the normal read operation to the memory circuit 6 corresponding to the internal address at this time is executed to read data based on this address. is checked by the error detection and correction circuit 8, and if there is no error as a result, a normal refresh operation is performed following this operation.

On the other hand, if a 1-bit error is detected in the error detection and correction circuit 8, the bit is corrected and then a normal write-in operation is performed, and this corrected data is sent to the same address again via the switch 2 and the error correction code generation circuit 4. This is written into the memory circuit, and then a normal refresh operation is performed.

If such a series of operations is performed for the entire address space of the memory circuit 6, soft errors can be relieved more effectively.

FIG. 2 is an example of a time chart of such an operation, where A is a refresh interrupt signal generated every cycle T1,
C is a read operation that contributes to soft error relief, and D
is an operation in which when a one-bit error is detected as a result of this read operation C, this bit is corrected and then data is written into the memory circuit again. E is a normal refresh operation, and F is a signal that receives the refresh interrupt signal of A and has a cycle that is an integral multiple (in this example, twice) of this signal (although it is not limited to this). G is an internal address signal that specifies the entire address space of the storage circuit by signal F, and has a period of 2T1 (generally NT1; N is an integer).
A binary addition is performed for each time.

B indicates the execution state in response to an operation request from an external device, and if it overlaps with a refresh operation, the command operation B from the outside is controlled by the refresh waiting circuit 17 for execution of other operations C to E. It is given priority. When the refresh operation is completed, the refrigerate signal A disappears.

In the figure, in the period a, an external operation is executed, followed by a read operation that contributes to soft error relief, and if there is no error in this operation, a normal refresh operation is subsequently performed. Period b is a case where only a normal refresh operation is performed, and during period C, there is a 1-bit error in a read operation that contributes to a soft error, and after this bit is corrected, a write operation is performed, and then a normal refresh is performed. In period d, there is an operation request from the outside, and after this operation is executed, normal refresh is executed.

By doing this, external processing i! This method avoids reducing the data transfer speed between the storage device and the storage device, and if a soft error occurs in an address area that is not accessed within the storage device, it will become an uncorrectable error if it overlaps with an intermittent error in other control systems, etc. The probability will decrease.

Effects of the Invention According to the present invention, data is read from the memory circuit every cycle that is an integer multiple of the refresh operation cycle and errors are detected, and if an error is detected, the error is corrected and a subsequent refresh operation is performed. This eliminates the need for sequence interrupt processing for normal operations in response to refresh requests, interrupt processing for temporary rewrite operations during one read operation, etc., and therefore does not cause a reduction in throughput between storage devices. Furthermore, it is possible to reduce the increase in the soft error occurrence rate in address areas that are not accessed within the storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of FIG. 1. Explanation of codes of main parts 4...Error correction code generation circuit 6...
Memory circuit 8...Error detection and correction circuit 13...
... Refresh control circuit 15 ... Internal address generation circuit 17 ... Refresh holding circuit 25 ... Invert multiplier circuit

Claims (1)

[Claims] a dynamic storage element; an error correction code generating means for adding an error correction code to write data and writing it into the storage element; and detecting the occurrence of a 1-bit error in read data from the storage element and correcting the error bit. and a refresh control means for controlling a refresh operation of the memory contents of the storage element, the storage device comprising: an error detection and correction means for controlling the memory contents of the memory element; It has a reading means for reading data from the storage element, and a writing means for instructing to write the corrected data to the storage element only when the read data has been error detected and corrected by the error detection and correction means. , the refresh control means:
A storage device characterized in that the storage device is configured to perform a refresh operation after the operations of the read means and the write means are completed, and to release the refresh interrupt request after the refresh operation is completed.