JPS61123957A - Storage device - Google Patents

Storage device

Info

Publication number
JPS61123957A
JPS61123957A JP59246500A JP24650084A JPS61123957A JP S61123957 A JPS61123957 A JP S61123957A JP 59246500 A JP59246500 A JP 59246500A JP 24650084 A JP24650084 A JP 24650084A JP S61123957 A JPS61123957 A JP S61123957A
Authority
JP
Japan
Prior art keywords
circuit
refresh
storage circuit
address
correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59246500A
Other languages
Japanese (ja)
Inventor
Kenji Ishikawa
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP59246500A priority Critical patent/JPS61123957A/en
Publication of JPS61123957A publication Critical patent/JPS61123957A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce soft errors by detecting the errors after reading total address space of a storage circuit every prescribed times period required for a refresh cycle, correcting these errors to write them in the storage circuit and shifting to refresh operation.
CONSTITUTION: After generating internal information through an address generating circuit 15 every period of integral times of refresh operation period, a normal reading is executed to a storage circuit 6 corresponding to the internal address. If there is no error, as a result of detecting the read data of this address by means of an error detecting/correcting circuit 8, normal refresh operation is executed in sequence. On the other hand, if one bit error is detected in the error detecting/correcting circuit 8, writing is executed after correcting the said bit, the corrected data is again written in the storage circuit of same address via a switch 2 and an error correction signal generating circuit 4, and then normal refresh operation is started. Thus it is possible to save the soft errors by above-mentioned sequential operations for total address space of the storage circuit 6.
COPYRIGHT: (C)1986,JPO&Japio
JP59246500A 1984-11-21 1984-11-21 Storage device Pending JPS61123957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59246500A JPS61123957A (en) 1984-11-21 1984-11-21 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59246500A JPS61123957A (en) 1984-11-21 1984-11-21 Storage device

Publications (1)

Publication Number Publication Date
JPS61123957A true JPS61123957A (en) 1986-06-11

Family

ID=17149317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59246500A Pending JPS61123957A (en) 1984-11-21 1984-11-21 Storage device

Country Status (1)

Country Link
JP (1) JPS61123957A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459842A (en) * 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
JP2012256414A (en) * 2011-06-09 2012-12-27 Samsung Electronics Co Ltd On-chip data scrubbing device including error correction circuit and method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143600A (en) * 1980-03-10 1981-11-09 Intel Corp Device for preventing accumulation of errors in data
JPS5782300A (en) * 1980-07-25 1982-05-22 Honeywell Inf Systems Dynamic memory system with software error rewriting control system
JPS5862891A (en) * 1981-10-09 1983-04-14 Fujitsu Ltd Memory rewrite system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56143600A (en) * 1980-03-10 1981-11-09 Intel Corp Device for preventing accumulation of errors in data
JPS5782300A (en) * 1980-07-25 1982-05-22 Honeywell Inf Systems Dynamic memory system with software error rewriting control system
JPS5862891A (en) * 1981-10-09 1983-04-14 Fujitsu Ltd Memory rewrite system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5459842A (en) * 1992-06-26 1995-10-17 International Business Machines Corporation System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
JP2012256414A (en) * 2011-06-09 2012-12-27 Samsung Electronics Co Ltd On-chip data scrubbing device including error correction circuit and method thereof

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