JPS5862891A - Memory rewrite system - Google Patents

Memory rewrite system

Info

Publication number
JPS5862891A
JPS5862891A JP56161262A JP16126281A JPS5862891A JP S5862891 A JPS5862891 A JP S5862891A JP 56161262 A JP56161262 A JP 56161262A JP 16126281 A JP16126281 A JP 16126281A JP S5862891 A JPS5862891 A JP S5862891A
Authority
JP
Japan
Prior art keywords
circuit
error
address
rewrite
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56161262A
Other languages
Japanese (ja)
Inventor
Kazuya Kobayashi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56161262A priority Critical patent/JPS5862891A/en
Publication of JPS5862891A publication Critical patent/JPS5862891A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Abstract

PURPOSE:To correct an error without dropping the use rate of a storage device, and to elevate reliability, by utilizing a refresh cycle of a dynamic memory element when an error is detected and rewrite is executed. CONSTITUTION:When an error read out from a storage device 5 is detected by an error detecting and correcting circuit 8, an error detecting signal is sent, and an error flag register 7 is set. At the same time, an error address holding circuit 6 is also set. When 3 conditions become complete, such as an error is generated from the register 7, an address sent out from a refresh controlling circuit 11 coincides with an address having an error by a coinciding circuit 9, and there is a refresh cycle from the circuit 11, an AND circuit 13 opens the gate, switches a switching circuit 2 and a switching circuit 4, to the circuit 6 side, and a data holding circuit 10 side which has received an error corrected data from the circuit 8, respectively, and also sends a write control signal by driving a timing controlling circuit 12. In this way, rewrite is executed.
JP56161262A 1981-10-09 1981-10-09 Memory rewrite system Pending JPS5862891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56161262A JPS5862891A (en) 1981-10-09 1981-10-09 Memory rewrite system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56161262A JPS5862891A (en) 1981-10-09 1981-10-09 Memory rewrite system

Publications (1)

Publication Number Publication Date
JPS5862891A true JPS5862891A (en) 1983-04-14

Family

ID=15731749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56161262A Pending JPS5862891A (en) 1981-10-09 1981-10-09 Memory rewrite system

Country Status (1)

Country Link
JP (1) JPS5862891A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61117788A (en) * 1984-11-13 1986-06-05 Fujitsu Ltd Method and device for refreshing and data checking of semiconductor memory
JPS61123957A (en) * 1984-11-21 1986-06-11 Nec Corp Storage device
US5055541A (en) * 1989-06-27 1991-10-08 Sequa Chemicals, Inc. Starch polymer graft composition and method of preparation
EP2455942A3 (en) * 2010-11-18 2013-01-09 Grandis, Inc. Memory write error correction circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61117788A (en) * 1984-11-13 1986-06-05 Fujitsu Ltd Method and device for refreshing and data checking of semiconductor memory
JPS61123957A (en) * 1984-11-21 1986-06-11 Nec Corp Storage device
US5055541A (en) * 1989-06-27 1991-10-08 Sequa Chemicals, Inc. Starch polymer graft composition and method of preparation
EP2455942A3 (en) * 2010-11-18 2013-01-09 Grandis, Inc. Memory write error correction circuit
US8456926B2 (en) 2010-11-18 2013-06-04 Grandis, Inc. Memory write error correction circuit

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