JPS58175197A - Main storage device - Google Patents

Abstract

PURPOSE:To recover a one-bit error due to a soft error to reduce the influence upon the degradation of capacity, by starting the cycle operation of read.modify.write or the like by a main storage device independently when the write operation is not performed for an error detection address within a prescribed time after detection of the one-bit error. CONSTITUTION:When a read operation request is issued to an address A20 including the error generation bit after the occurrence of the soft error, a one- bit error detection signal 211 is outputted, and the address A20 is latched as an error recovery address 213 in a flip flop 212a, and a timer circuit 221a is started. If a write operation request is not issued to the address A20, where the one-bit error is detected in the read operation, within a time TS after the output of the one-bit error detection signal 211, the timer circuit 221a outputs an error recovering operation start signal 220, and an error recovering operation cycle is started to recover the soft error.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory device having a plurality of memory banks capable of independently executing memory cycles, and more specifically to a main memory device capable of controlling recovery of a 1-bit error caused by a soft error.

FIG. 1 is a circuit block diagram showing an example of the main memory device.

A conventional main memory device can be roughly divided into its components, as shown in FIG. 1, a storage section 110 consisting of a plurality of memory banks 111 that can independently execute memory cycles, and connecting devices such as a central processing unit. The control unit 120 performs predetermined m control based on memory access requests from the memory access request.

Furthermore, the storage unit 110 is constituted by a plurality of memory units 112t and four memory banks 111 according to their storage capacities.

On the other hand, the control unit 120 receives a reception interface signal 121 such as an address, write data, and operation designation information sent in response to a memo 1J access request from a connected device.
) transmission interface signal 12 such as read data, etc.
2, and the storage unit 110 in response to an operation activation signal 124 such as an address and operation designation information from this interface transmission and reception unit 123.
A main control section 127 supplies a memory section control signal 125 such as a memory section address or an address strobe signal to the corresponding bank, and supplies an operation control signal 126 to each section in the control section, and a main control section 127 supplies the operation start signal 124 to the corresponding bank. When a write operation is specified, a check bit is generated based on the write data 127 from the interface transmitting/receiving section 123, and a check bit consisting of the write data and the check bit is generated for the corresponding memory bank 111 of the storage section 110. Write information 1
28, and in the case of a read operation, errors are detected and corrected based on the read information 129 from the corresponding memory bank 111 of the storage unit 110, and then read data 130 is sent to the interface transmitting/receiving unit 123. Control unit 1
As the memory element constituting the memory unit 110, dynamic type MO8RAM is widely used in terms of price and storage capacity.
A book enclosed in an LSI package (In1ine Package) type is used.

As is well known, most of these LSI packaging materials emit ionizing radiation called alpha rays, to varying degrees, and are capable of reversing the charge stored in the cells, which are the units of information in RAM chips. It may cause
Therefore, when a read operation request is received from the connected device to the main memory device for an address including a cell whose information has been inverted by alpha rays, the data control unit 131 detects a data error.

This error is not a permanent physical defect called an error, but is a soft error that can be completely repaired by the next write operation.

Generally, one word, which is a read unit of read information 129 from storage unit 110, is composed of a plurality of bits. KashiniR
Assuming that the read data width of one AM chip is 1 bit, the number of RAM chips equal to the number of bits constituting one word is required. As mentioned above, soft errors that occur when one word is composed of multiple RAM chips have a very small probability of occurring in two or more locations within the same word, and most of them occur in one R or AM chip. It is known that the probability of occurrence is

Therefore, when a read operation is performed on this error occurrence address after a soft error occurs, the read information 129 from the storage unit 110 is input to the data control unit 131 with one bit inverted. At step 131, 1-bit error is detected and corrected for the read information 129, so that error-free read data can be sent to the connected device that has issued the 1-read operation request. However, the memory part 1
The soft errors within 10 remain unrepaired, and after this, another bit in the word containing the soft error is
When a doler occurs, a 2-bit error is detected during the read operation of the address where the error occurred. Since 2-bit errors are impossible to correct in this type of main memory, the occurrence of 2-bit errors will lead to system failure.

As mentioned above, in a main memory device like the one shown in the IEI diagram, if a soft error occurs in the RAM chip that makes up the memory section, and then a hard error occurs in another bit of the same word, the address where this error occurred will be There is a drawback that a 2-bit error is detected when an operation request is received from a connected device such as a central processing unit, leading to a system down.

In addition, in conventional systems, there is a method to repair soft errors by periodically refreshing the contents of the main memory storage section by reloading it from disk, but in this case, the connected device is the main This has the disadvantage that it takes up a lot of time on the storage device, leading to a significant drop in system performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a main memory device that reduces the probability of a 2-bit error occurring and also reduces the impact of soft error recovery on performance degradation.

The storage device has a storage section consisting of a plurality of punctures that can independently execute memory cycles in response to operation requests from connected equipment such as a central processing unit, and detects and corrects errors in data when reading from this storage section. In a main memory having a function as a part of the control unit, the main memory is provided for each puncture or for a predetermined number of punctures, and when receiving the signal indicating the detection of the 1-bit error, the access address associated with the operation request is provided. error address storage means for inputting and holding the error address as an error address, and selectively outputting either the error address held in the error address storage means provided for each bank or an access address accompanying an operation request from a connected device. address selection means for supplying to the storage unit and the error address storage means are provided for each of the error address storage means, and the access address accompanying the operation request from the connected device matches the error address held in the error address storage means; When a signal indicating that the operation request is an operation involving writing to a storage unit is input,
address match detection means for outputting an address match signal;
A timer is provided for each of the address match detection means, and starts a timer when receiving a signal indicating the detection of a 1-bit error, and the address match detection signal is not input before the timer ticks a fixed time as a monitoring time. At this time, a signal for causing the address selection means to selectively output an error address for a certain period of time, a signal for causing the address selection means to select and output an error address, and a series of signals for causing the address selection means to read from this error address and writing data obtained by correcting the error of the read data to the same address. Error repair operation activation means for activating the operation and outputting a signal for suppressing operation requests from connected devices at least during this operation period is added.

According to the above configuration, the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the main memory device according to the present invention.

In this embodiment, a storage section 110 and a control section 120 having the same functions as the first section are provided, and each bank of the storage section 110 is provided with a readout operation for an access address 210 based on a request from a connected device such as a central processing unit. In the storage unit 110
Read information from corresponding memory puncture 111 @ 129 to 1
When a bit error is detected, the access address 2
10 is a 1-bit factory detection signal 211 for puncture protection.
Error address storage means 2 for holding input under the control of
12, an error recovery address 213 which is provided for each bank of the storage section 110 and is an output from the error address storage means 212, and the access address 210, and one of them is inputted to the storage section control in FIG. Address selection means 215 selectively outputs one of the signals 125 as the address signal 214 of the storage unit 110, and is provided for each node of the storage unit 110, and a write operation is activated by a request from a connected device. 7 that is sometimes output from the control unit 120
A write operation start signal 216 corresponding to 9-bit write operation, the access address 210 and error recovery address 213 associated with this write operation are input, and the access address 210 and error recovery address 213 when the write operation is started are input. address match detection means 218 which outputs an address match signal 217 when the addresses match; an address selection signal 219 that causes the address selection means 215 to select and output the error repair address 213 when the address matching signal 217 is not input within a possible time;
and the main storage device independently performs a read operation from the error recovery address 213 without a request from the connected device, and 1 of the read information 129 read due to the malfunction.
Error correction starts a series of operations in which bit error correction is performed and the error-corrected data is rewritten to the same address as write information 128, and operation requests from connected MUs are suppressed during this operation period. and an error repair operation activation means 221 that supplies an operation activation signal 220 to the control section 120.

FIG. 3 is a diagram showing details of the main storage device shown in FIG. 2. This figure shows an error address storage means 212, an address match detection means 218, and an error repair one operation starting means 221.
This figure shows an embodiment of the circuit constituting the address selection means 215, and since there is no difference between banks, the circuit for one arbitrary bank is extracted.

In the following description of FIG. 3, it is assumed that the device employing the present invention is a so-called clock synchronous type device that operates with a clock φ having a cycle that is an integer fraction of the operating cycle Tc.

In FIG. 3, the error address storage means 212 is composed of a D-type flip-flop 212a, and when the 1-bit error detection signal 211 that performs hold control of this flip-flop becomes logic 'I', the edge of the clock φ is latches the access address 210.

The address-scattering product output circuit 218 is an exclusive OR circuit 218
& and an AND circuit 218b, and when a write operation start signal 216 is output by a write operation to the access address 210, the access address 21
It is detected whether or not the error repair address 213 which is set in the above 7 lip-flops 212a and Vc5 matches.

The error repair operation starting means 221 is a timer circuit 221a1.
It is composed of a shift register 221b and an OR circuit 221C. The timer circuit 221a is activated by the 1-bit error detection signal 211 and monitors for a certain period of time. The time for performing this monitoring can be set to an arbitrary value Tslc.

The timer circuit 221a outputs the address match signal 2 within the monitoring time T1 after the 1-bit error detection signal 211 is input.
17 is not input, the error repair operation activation signal 220
Output. This error repair operation activation signal 220 is input to the control unit 1201 shift register 221b and OR circuit 221C, and the former activates a so-called read-modify-write operation and also suppresses operation requests from connected devices during this operation. This is the error repair operation activation signal. The latter is an address selection signal 219 that selects and outputs the storage address 214 to be accessed during a read/modify/write operation, and in this case, it is a signal with a time width that is an integral multiple of the clock. The error recovery address 213 is supplied for a certain period of time.

Note that the read/modify/write operation described above is a sequence of reading data from a specified address in the storage unit, and then rewriting the data with error correction of the read data to the same address. This means that the following operations are performed within one cycle.

The address selection means 215 uses two manual selection circuits 215a, one access address 210 and one error recovery address 21.
3 is input, and one of them is selected and output by the address selection signal 219.

4 and 5 are time charts for explaining the operation of FIG. 3. FIG.

Figures 4 and 5 show 1 caused by a soft error.
After detecting a bit error, tie 1 circuit 221 JL
This corresponds to the case where a write operation occurs to an address that matches this error address within a certain time Ts when K is set, and the case where there is no write operation, respectively.

First, the operation in FIG. 3 will be explained based on FIG. 4.

After a soft error occurs, when a read operation cycle is started in response to a request from a connected device for the address AIO containing the error occurrence bit, a 1-bit error is detected in the read data, and a 1-bit error detection signal 211 is output.

1 bit x error detection signal 211
is latched by the flip-flop 212aK as the address 213 of the address 213, and the timer circuit 221 &
is started. The time Twl (Ts>Twt) after the 1-bit error detection signal 211 is output
), if there is a write operation request for address All, a write operation start signal 216 is output, but the error recovery address 213 (AIO') latched in the clip-flop 212a and the access address 210 (AIO') are output.
1), the exclusive OR circuit 2181 cannot find a match, so the address match signal 217 is not output and the tie 1 circuit 2
21a The Holy Night continues by K. Furthermore, when a write operation request is made to the same address AIO as the read operation after time Twz (Ts Twz) has elapsed, a write operation start signal 216 is output, and the error recovery address 213 (A10) and access address 210 are output.
(Person 10) is -t, so the address match signal 217
is output.

By this address match signal 217, the timer circuit 221
Since a is reset, the address selection signal 219 and the error repair operation activation signal 22G are not output.

Next, the operation of FIG. 3 will be explained based on FIG.
The bit error detection signal 211 is output, and A20 is set as the error recovery address 213 to the flip-flop 212a.
is latched, and the timer circuit 221 is activated.

In the case of this figure, a write operation request is not received for address A20 where a 1-bit error was detected in the read operation within time T after the 1-bit error detection signal 211 is output, so the timer circuit 221 m outputs an error repair operation start signal 220 to start an error repair operation cycle. It is appropriate that this error recovery operation cycle be performed using the read-modify-write operation that this type of main memory device normally has, and to ensure the execution of this operation, the connection during this operation period is Suppress operation requests from devices.

Further, inputting the error repair operation activation signal 220 to the shift register 221b and the OR circuit 221c.
Therefore, an address selection signal 219 is generated, and the error repair address 213 (A
20) is selectively output.

By the above operation, read/modify/write is activated for the address (A20) where a 1-bit error is detected, and the soft error is repaired.

In the above explanation, the error address storage means 212
Although an example has been described in which the address match detection means 218 and the error repair operation activation means 221 are provided for each bank, it is also possible to share the above circuit among a plurality of punctures.

FIG. 6 shows an embodiment in which the above circuit is shared between two banks. The difference from FIG. 3 is that the error address storage means 212 includes two manual selection circuits 212b and an OR circuit 2.
12C, an exclusive OR circuit 218C, an AND circuit 218d, and an OR circuit 2 in the address match detection means 218.
18., the error repair operation starting means 221 includes an OR circuit 221d, a flip-flop 221e, and an AND circuit 22.
1f and 221g were added.

The operation of each circuit is the same as that shown in Figure 3, so the explanation will be omitted.
In particular, the two-manpower circuit 212b is a circuit that selects and outputs the access address when a 1-bit error is detected by the corresponding machine puncture, and the OR circuits 212C and 221d are circuits that detect that there is an error in either one of the input banks. The flip processor 7'221e is a circuit that latches 1-bit error detection for each bank, and is a circuit that determines the bank at the time of starting the Sheller repair operation using AND circuits 221f and 221g.

As explained in detail above, the main memory device according to the present invention is
If a write operation is not performed to the error detection address within a specified time after a 1-bit error is detected, the main memory device independently starts cycle operations such as read, modify, and write. By repairing a 1-bit error, it is possible to reduce the probability that another 1-bit hard error in the same word will lead to a 2-bit error, and to reduce the impact of soft error repair on performance degradation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional main storage device, FIG. 2 is a diagram showing a first embodiment of the main storage device according to the present invention, FIG. 3 is a diagram showing details of FIG. 2, and FIG. Figure 4 and taS diagram are the third
A time chart for explaining the operation shown in FIG. 6 is a diagram showing an embodiment of the present invention. 110...Memory m 111...Memory bank 112...Memory unit 120...Control unit 1
21...Receiving interface signal 122...Transmitting interface signal 123...Interface transmitting/receiving section 124...Operation start signal 125...Storage section f control signal 126...Operation control signal 127...Write Data 128...Write information 129...Read information 1
30... Read data 131... Data control section 2
10...Access address 211...1-bit factory detection signal 212...Error address storage means 212a...Flip flow knob 212b--2Manual selection circuit 2120% 218es 221es 221d'=
OR circuit 213...Error repair address 214...Storage unit address signal 215...Address selector R 216...Write operation start signal 215tL...2 manual selection circuit 217--Address match signal 21B . . . address - scatter product output means 218aS218c = exclusive wk logic circuit 218b
, 2L8d % 22Lf , 221g...AND circuit 219...Address selection signal 220...Error repair operation starting signal 221...Error repair operation starting means 221a...Timer circuit 221b...Shift register 221e ...Flip-flop patent applicant NEC Corporation Kinsha

Claims (1)

[Claims] It has a memory section consisting of multiple banks that can independently execute memory cycles in response to operation requests from connected devices such as a central processing unit, and controls the function of detecting and correcting data errors during read operations from this memory section. A main memory device provided in a part of the unit is provided for each bank or for a predetermined number of banks, and upon receiving a signal indicating the detection of a 1-bit error, converts the access address associated with the operation request to an error address. an error address storage means for inputting and holding the error address; and an address selection means for selectively outputting either the error address held in the error address storage means or an access address accompanying an operation request from a connected device and supplying it to the storage unit. , provided for each of the error address storage means, the access address associated with the operation request from the connected device matches the error address held in the error address storage means, and the operation request does not require writing to the storage unit. an address coincidence detection means that outputs an address coincidence signal when a signal indicating that the 1-bit error is detected is input; 1. When the address matching detection signal is not input before this timer ticks a fixed time as a monitoring time, a signal is generated that causes the address selection means to select and output an error address for a fixed period of time, and reads from this error address. - Starts a series of operations to write error-corrected data to the same address, and outputs a signal to suppress operation requests from connected devices at least during this operation period. a main memory device further comprising an error repair operation activation means for