JP2000163320A - Memory device with software error measure function and software error measure method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device having software error measure function and a software error measure method with which improvement in the performance of the memory device can be expected while efficiently using a bus line by adding a software error measure function to the device. SOLUTION: This device has a memory cell array 11 having at least three memory cells A, B and C for storing data and a majority decision circuit for selecting data in the memory cell, which is not affected by a software error, according to a majority decision concerning the stored contents of the respective memory cells A, B and C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a soft error countermeasure technology and a memory device, and more particularly, to a memory device having a soft error countermeasure function, whereby a bus line can be used efficiently and an improvement in device performance can be expected. The present invention relates to a memory device having a soft error countermeasure function and a soft error countermeasure method.

[0002]

2. Description of the Related Art In recent years, as memories have become more highly integrated, the volume of memory cells has become smaller, and the problem of soft errors caused by alpha rays latent on the ground or particles existing in outer space has become apparent. . Soft error refers to a phenomenon in which the content recorded by α rays or neutrons existing on the ground is inverted in bit units. Particularly in outer space, this soft error frequently occurs due to heavy particles emitted from the sun, particles captured by the earth, or particles flying from outer space. As a countermeasure against this soft error, conventional techniques such as Huffman coding corresponding to a 1-bit error or Reed-Solomon coding for correcting an error in word units are known.

[0003]

However, in these prior arts, a countermeasure against soft errors is executed by adding an external device. In addition, for on-board satellite equipment where the weight of the equipment is a problem, the cyclic design of the memory is processed by software in order to prevent the occurrence of two-bit errors in one word, so that one-bit error correction is performed. Because of the burden, the performance of the apparatus is limited. The present invention has been made in view of such a problem, and an object of the present invention is to provide a memory device with a soft error countermeasure function by alleviating such a constraint condition so that a bus line can be efficiently provided. It is another object of the present invention to provide a memory device with a soft error countermeasure function and a soft error countermeasure method, which can be used to improve device performance.

[0004]

The gist of the present invention resides in a soft error countermeasure for judging a soft error of a memory cell and selectively outputting data judged not to have suffered a soft error. A memory device with a function, comprising: a memory cell array having at least three or more memory cells for storing data; and executing a majority process on the storage contents of each of the three or more memory cells to reduce a soft error. And a majority decision circuit for selecting uncovered data. The gist of claim 2 of the present invention is that, when the majority circuit determines that the storage content of any one of the three or more memory cells has suffered a soft error, 2. The software according to claim 1, wherein the memory contents other than the memory cells are selected so as to execute a selection process using majority logic that determines that the memory contents of the memory cells do not suffer from a soft error. It exists in a memory device with an error countermeasure function. The gist of claim 3 of the present invention is that the majority circuit is provided in the same number as the number of the memory cells, and compares two stored contents read out from each of the memory cells in a round robin set. 3. The memory device with a soft error countermeasure function according to claim 2, further comprising compare means for performing a majority comparison. The gist of claim 4 of the present invention is that, when the memory contents are different between the two memory cells set in a brute force set, the majority decision circuit sets the two memory cells in a brute force set. The memory contents other than the memory cell that has not been determined to have not suffered a soft error, the memory cell determined to have not suffered the soft error is selected as a memory cell to be output, and the selected memory cell is selected. 3. The apparatus according to claim 2, further comprising word selector means configured to output the stored contents of
Or the memory device with soft error countermeasure function described in 3. The gist of claim 5 of the present invention is that, when the storage unit outputs the storage content in word units defined by a predetermined bit length from each of the memory cells,
5. The storage system according to claim 3, wherein the stored contents are configured to perform the majority comparison in word units.
The memory device with a soft error countermeasure function according to any one of the above. The gist of claim 6 of the present invention is:
4. The comparison means according to claim 3, wherein when the storage content is output from each of the memory cells with a predetermined bit length, the storage content is subjected to the majority comparison in bit units. 5. The memory device with a soft error countermeasure function according to any one of the above items 4 to 4. Further, the gist of the present invention is that each of the compare means outputs a signal of a logical value H when the storage content of the memory cell that has performed the majority comparison is correct, and executes the majority comparison. And outputting a signal having a logical value L when the stored content of the memory cell is incorrect. The word selector means outputs an output signal from each of the compare means and an output signal from each of the three or more memory cells. A memory cell designated by a logical value H is selected as a memory cell having a correct storage content using the stored storage content, and the storage content instructs to output a storage content of the correct memory cell. 5. The memory device with a soft error countermeasure function according to claim 4, wherein The gist of claim 8 of the present invention is that the storage contents of the memory cells not suffering from the soft error received from the word selector means are received at a timing of writing back to the same address or at a timing externally controlled. Re-entering at least the data input end of the memory cell suffering the soft error and rewriting the memory contents of the memory cell suffering the soft error to the memory contents of the memory cell not suffering the soft error; The memory device with a soft error countermeasure function according to any one of claims 1 to 7, further comprising updating means for executing a process. According to a ninth aspect of the present invention, there is provided a soft error countermeasure method for determining a soft error of a memory cell and selectively outputting data determined to be free from the soft error. A majority memory process for storing data in the above memory cells,
A majority decision step of executing a majority decision process on the storage contents of each of the three or more memory cells to select data free from a soft error. The gist of claim 10 of the present invention is that when the majority decision step determines that the storage content of any one of the three or more memory cells has suffered a soft error, 10. The soft error countermeasure method according to claim 9, wherein a selection process using majority logic is performed to determine that the memory contents of the remaining memory cells except for the memory cell are free from a soft error. According to another aspect of the present invention, in the majority decision step, the same number as the number of the memory cells is provided, and two sets of stored contents read from each of the memory cells are compared in a round robin set. 11. A comparing step for performing a majority comparison.
In the soft error countermeasures described in (1). Further, the gist of the twelfth aspect of the present invention is that the majority decision step includes the step
When the memory contents are different between the memory cells in the brute force set, it is determined that the memory contents of the memory cells other than the memory cells in the two brute force sets have not suffered a soft error. 11. A word selector step for selecting a memory cell determined not to have suffered the soft error as a memory cell to be output and outputting a storage content of the selected memory cell. There is a soft error countermeasure method described in No. 11. The gist of claim 13 of the present invention is that, when the storage content is output in word units defined by a predetermined bit length from each of the memory cells, the storage content is written in word units. The soft error countermeasure method according to claim 11, wherein a majority comparison is performed. According to another aspect of the present invention, in the comparing step, when the storage content is output from each of the memory cells in a predetermined bit length, the majority comparison is performed in bit units on the storage content. A soft error countermeasure method according to any one of claims 11 to 12, characterized in that: The gist of claim 15 of the present invention is that each of the compare steps outputs a signal of a logical value H when the storage content of the memory cell that has performed the majority comparison is correct, and executes the majority comparison. And outputting a signal having a logical value L when the stored content of the memory cell is incorrect. The word selector step includes an output signal from each of the compare steps and an output signal from each of the three or more memory cells. A memory cell designated by a logical value H is selected as a memory cell having a correct storage content using the stored storage content, and the storage content instructs to output a storage content of the correct memory cell. The soft error countermeasure method described in No. 12. The gist of claim 16 of the present invention is that at a timing of writing back to the same address or at a timing controlled from the outside, the storage contents of the memory cells not suffering from the soft error received from the word selector process are stored. Re-entering at least the data input end of the memory cell suffering the soft error and rewriting the memory contents of the memory cell suffering the soft error to the memory contents of the memory cell not suffering the soft error; The method according to any one of claims 9 to 15, further comprising an update step for executing a process.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Soft error refers to a phenomenon in which the contents recorded by α rays or neutrons existing on the ground are inverted in bit units. Particularly in space, this soft error frequently occurs due to heavy particles emitted from the sun, particles captured by the earth, or particles flying from space. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the first and second embodiments, the memory device with a soft error countermeasure function is provided with this countermeasure, and outputs data having as few bit errors as possible by the soft error countermeasure.

FIG. 1 is a system block diagram for explaining one embodiment of a memory device with a soft error countermeasure function and a soft error countermeasure method according to the first and second embodiments. A feature of the first and second embodiments is that the memory cell array 11 includes three memory cells A, B, and C and has a common address, so that the same data is stored in each of the memory cell arrays A, B. , C. When the timing condition for outputting the data is satisfied, the data is compared by 4-bit word compares 15, 16, and 17 (subject executing the compare process) via the lower shift register, and it is determined whether or not the data is the same. The determination result is input to the word selector 18 (subject of executing the word selector step) as a select signal indicating which cell data is to be believed by the word selector 18.
In response, the word selector 18 selects and outputs the data of the memory cell to be output. The majority function is performed by a majority circuit. Here, what is important as an algorithm is to provide a majority function that determines that the contents of the remaining two memory cells are correct if the storage contents of any one of the three memory cells A, B, and C are incorrect. That is. As a method of taking a majority vote in the majority function, a method of comparing in word units or bit units is also possible.

(First Embodiment) A memory device with a soft error countermeasure function according to a first embodiment includes a memory cell array 11 for executing a majority memory step, a logic circuit for reading / writing the memory cell array 11, and a majority step. It has a majority decision circuit to execute. In this embodiment, a dynamic RA is used as a memory device having a soft error countermeasure function.
This will be described using M as an example. The read / write logic circuit includes a / RAS clock generation circuit 1, a / CAS clock generation circuit 2, a / WE clock generation circuit 3, a refresh control address counter 4, an address buffer 5, a column decoder 6, a row It comprises a decoder 7, a sense amplifier 8, a Din buffer 10, and an output switch 19. The logic circuit does not take a special circuit, but is a circuit which can be easily realized. The majority circuit is a circuit that determines that the contents of the remaining two memory cells are correct if the memory cell array 11 among the three memory cells A, B, and C is incorrect. The majority circuit is an I / O switch and 4-bit latch circuit 9 (update process). Executing entity), 3
Four 4-bit latch circuits 12, 13, 14, three 4b
It has an it word compare 15, 16, 17 and a word selector 18.

Each of the three memory cells A, B, and C constituting the memory cell array 11 stores data in accordance with an address indicating a storage location. The read / write control signals determined by the type of the memory element include:
For example, W to be activated at the timing of writing
E, OE to be activated at the output timing, and the like.

In particular, the dynamic RAM has a multi-bit address (for example, a 32-bit address → 64).
(Addressing of bit configuration), matrix-type addressing composed of columns and rows is used, and complex addressing is performed by using a column address strobe control signal CAS or a row address strobe control signal RAS. The read / write control is executed at an appropriate timing. In addition, it is necessary to perform control for recharging the charged electric charge within a short holding time by an operation called refresh. The control method for such read / write differs depending on the memory system of the dynamic RAM. In the memory device with a soft error countermeasure function of the present embodiment, a memory cell array 11 for storing data and a circuit for taking a majority decision on the stored contents of the three memory cells A, B, and C of the memory cell array 11 are added. However, since the read / write control method is the same as that of the prior art, it can be applied to any type of semiconductor storage device including a RAM.

On the other hand, each of the three memory cells A, B, and C is connected to the three 4-bit latch circuits 12, 13, and 14 on a one-to-one basis. Specifically, the output of the memory cell A is connected one-to-one to the input of the 4-bit latch circuit 14, the output of the memory cell B is connected one-to-one to the input of the 4-bit latch circuit 13, and the output of the memory cell C is 4 bits
The input of the latch circuit 12 is connected one-to-one. The output of the 4-bit latch circuit 12 (output of a 4-bit configuration) is connected in parallel to the inputs of two 4-bit word compare units 15 and 17 and the input of the word selector 18 and
The output of the it latch circuit 13 (output of 4-bit configuration) is 2
The inputs of the four 4-bit word compares 15 and 16 and the input of the word selector 18 are connected in parallel.
It is connected in parallel to the inputs of the it word compare 16, 17 and the input of the word selector 18. Output of 4-bit word compare 15 (denoted as B selection in the figure), 4 bits
The output of the word compare 16 (denoted by A selection in the figure) and the output of the 4-bit word compare 17 (denoted by C selection in the figure) are connected to the input of the word selector 18.

The memory cell array 11 provided in the memory device with a soft error countermeasure function according to the present embodiment has the same configuration having a common address (8-bit address of A0,..., A7) (that is, the address bus has a common configuration). ) Are provided. Therefore, at the time of writing (that is, when no soft error has occurred at this time), the 4-bit data held in each of the three memory cells A, B, and C has the same logical value.

The 4-bit data held in each of the three memory cells A, B, and C has a possibility of being erroneous in units of bits (a possibility of causing a soft error) due to flying particles. Therefore, in the present embodiment, the data held in one memory cell (for example, memory cell A) of the 4-bit data held in each of the three memory cells A, B, and C causes a soft error. Even if they do, it is assumed that the other two memory cells (in this case, B and C) are erroneously mistaken at the same time, and that the probability is considerably low and that there is substantially no problem. Based on such an assumption, by using the memory device with a soft error countermeasure function and the soft error countermeasure method of the present embodiment, a soft error occurs in any one of the three memory cells A, B, and C. Also, by selecting the other two memory cells in which the soft error has not occurred (that is, by removing the data of the memory cell in which the soft error has occurred by executing the selection process using majority logic). ), It is possible to output data in which no soft error has occurred.

The method of selecting the other two memory cells in which the soft error has not occurred (that is, the method of eliminating the data in the memory cell in which the soft error has occurred by selection using majority vote) is performed by using three memory cells. A, B, C
The 4-bit data held in each of the three memory cells A, B, and C obtained via the three 4-bit latch circuits 12, 13, and 14 connected one-to-one to
This can be realized by comparison using three 4-bit word compares 15, 16, and 17. That is, the 4-bit word comparison between the 4-bit data held in the memory cell C obtained via the 4-bit latch circuit 12 and the 4-bit data held in the memory cell B obtained via the 4-bit latch circuit 13 is performed. 15, the 4-bit data held in the memory cell B obtained via the 4-bit latch circuit 13 and the 4-bit data held in the memory cell A obtained via the 4-bit latch circuit 14 are compared. Compared by 4-bit word compare 16, 4bi
The 4-bit data held in the memory cell C obtained via the t-latch circuit 12 and the 4-bit latch circuit 14
The 4-bit word compare 17 compares the 4-bit data held in the memory cell A obtained via the memory cell A with the memory cell A, thereby realizing the selection processing using the majority logic described above.

The above-described selection processing using majority logic is, specifically, performed by three 4-bit word compares 15, 16,.
17, the read data from the three memory cells A, B, and C are compared every two in a brute force set. If the two memory cells have different values, the other memory cells ( That is, the data of the memory cell to be output is selected by the word selector 18 that specifies the remaining one of the three memory cells.

Next, the operation of the majority circuit of the first embodiment will be described. The data of the memory cell A is output to the 4-bit latch circuit 14 simultaneously with the data output from each of the other two memory cells B and C. The data of the memory cell B is output to the 4-bit latch circuit 13 simultaneously with the data output from each of the other two memory cells A and C. Memory cell C
Is output to the 4-bit latch circuit 12 simultaneously with the data output from each of the other two memory cells A and B. 4b simultaneously from each of three memory cells A, B, C
The respective data output to the it latch circuits 12, 13, and 14 are compared in word units (1 word = 4 bits) by 4-bit word compares 15, 16, and 17. The word unit is 8 bits or 16 bits in addition to 4 bits.
Obviously, it may be a bit or the like.

4 bit word compare 15, 16, 17
Output a signal of a logical value H when the storage content of the compared memory cell is correct, and output a signal of a logical value L when the storage content of the compared memory cell is incorrect.
The word selector 18 has a 4-bit word compare 15,
The output signal from each of the memory cells 16 and 17 and the output data of each of the three memory cells A, B and C (the stored contents)
Is used to execute the following determination, and the result of the determination is output. 1. If the storage content of the memory cell A is correct (logical value H), a signal for selecting the memory cell A is output to the I / O switch & 4-bit latch circuit 9 regardless of the storage content of the memory cells B and C. 2. When the storage content of the memory cell B is correct (logical value H), a signal for selecting the memory cell B is output to the I / O switch & 4-bit latch circuit 9 regardless of the storage content of the memory cells A and C. 3. When the storage content of the memory cell C is correct (logical value H), a signal for selecting the memory cell C is output to the I / O switch & 4-bit latch circuit 9 regardless of the storage content of the memory cells A and B. 4. If the storage contents of each of the three memory cells A, B, and C are all incorrect (logical value L), the signal of the bit majority result (or ALL “H”) is sent to the I / O switch &
Output to the 4-bit latch circuit 9.

Basically, three memory cells A, B, C
Cannot be considered as logical values L, but it is necessary to determine the logic in such a case. In the specification on the ground, this logic may be omitted, or the logic may be selected as one for simplifying the configuration. Memory devices with soft error countermeasures
In this way, data without soft errors can be output. In addition, since data without a soft error is fed back to the input of the memory cell that has suffered a soft error, the storage data of the memory cell that has suffered a soft error is rewritten to correct data (soft error recovery processing). Can be corrected. This is because it is only necessary to specify the address and select the word select, and then perform the control of returning to the cell without making / OE and / WE active. When the timing accesses the entire address in order, the timing can be diverted and the I / O switch & 4-bit latch circuit 9 can be easily realized by selecting the data on the word selector 18 side.

In a memory device having a soft error countermeasure function for executing such a soft error countermeasure method, a conventional EC device is used.
The C circuit becomes unnecessary. Soft errors can be avoided in the memory cell array 11. Further, at the timing of writing back to the same address or externally (specifically, / WE
At the timing controlled by the clock generation circuit 3), the output data of the memory cell not suffering the soft error (the output storage content) is input via the word selector 18 at least to the data input of the memory cell suffering the soft error. This makes it possible to realize a soft error recovery process of re-inputting to the end (in other words, a soft error recovery process of rewriting data that has not suffered a soft error). As a result, the occurrence of an error of one bit or more can be suppressed to an extremely low probability. As a result, space-borne equipment that has a high probability of bit errors can reduce the hardware and software required for countermeasures to recover from soft errors, and conserve hardware and software resources for space-borne equipment. It is possible to effectively allocate to the original work, and it is possible to improve the processing performance of the device.

(Second Embodiment) In the majority circuit of the second embodiment, each data output from the three memory cells A, B, and C to the 4-bit latch circuits 12, 13, and 14 at the same time is a 4-bit word. Compare 15, 16, 17
Is characterized in that output data (outputted storage contents) of each memory cell is compared in bit units.
Also, the majority voting method performed in units of words as in the first embodiment and the majority voting method performed in units of bits as in the second embodiment can be selectively used depending on the application.

In the present embodiment, the present invention is not limited to a dynamic RAM, and various types of memories (for example, synchronous D memories) suitable for applying the present invention.
The present invention can be applied to a semiconductor storage device such as a RAM and an EEPROM. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention.

[0021]

Since the present invention is configured as described above, the following effects can be obtained. First, conventional ECC
The 1-bit correction function by the circuit becomes unnecessary. as a result,
A memory for code data is not required. Second, periodic one-bit correction in which no two-bit error occurs can be performed in the memory, thereby contributing to improvement in device performance (higher processing speed, etc.). Third, since the soft error countermeasure function can be mixedly mounted in the chip, the space of the device can be saved, and the memory density and the memory capacity can be easily increased. If the data cannot be stored in the same chip, the chip size package (CSP: Chip Scale) is combined with the memory device having the soft error countermeasure function.
(Package) and can be realized as an MMIC or a memory module.

[Brief description of the drawings]

FIG. 1 is a system block diagram for explaining an embodiment of a memory device with a soft error countermeasure function and a soft error countermeasure method of the present invention.

[Explanation of symbols]

1 ... / RAS clock generation circuit (logic circuit for read / write) 2 ... / CAS clock generation circuit (logic circuit for read / write) 3 ... / WE clock generation circuit (logic circuit for read / write) 4 ... Refresh control address counter (logic circuit for read / write) 5 ... Address buffer (logic circuit for read / write) 6 ... Column decoder (logic circuit for read / write) 7 ... Row decoder (read) / Logic circuit for write / write 8 ... Sense amplifier (logic circuit for read / write) 9 ... I / O switch & 4-bit latch circuit (majority decision circuit (update means)) 10 ... Din buffer (logic circuit for read / write) 11) Memory cell array 12 ... 4-bit latch circuit (majority decision circuit) 3 ... 4 bit latch circuit (majority decision circuit) 14 ... 4 bit latch circuit (majority decision circuit) 15 ... 4 bit word compare (majority decision circuit (compare means)) 16 ... 4 bit word compare (majority decision circuit (compare means)) 17 ... 4 bit word compare ( Majority circuit (compare means) 18 word selector (major circuit (word selector means) 19 output switch (logic circuit for read / write) A, B, C memory cells

Claims (16)

[Claims] 1. A memory device having a soft error countermeasure function for judging a soft error of a memory cell and selectively outputting data judged to be free from a soft error, wherein at least three memory devices for storing data are provided. A memory cell array including the above memory cells; and a majority circuit for executing majority processing on the storage contents of each of the three or more memory cells to select data free from a soft error. Memory device with soft error countermeasure function. 2. When the majority circuit determines that the storage content of any one of the three or more memory cells has suffered a soft error, the majority circuit excludes the remaining memory cells excluding the memory cell. 2. The memory device with a soft error countermeasure function according to claim 1, wherein the memory device is configured to execute a selection process using a majority decision logic that determines that a memory content of the memory cell does not suffer from a soft error. 3. The majority circuit has a compare means provided in the same number as the number of the memory cells and performing a majority comparison in which two stored contents read from each of the memory cells are compared in a brute force set. 3. The memory device with a soft error countermeasure function according to claim 2, wherein: 4. The majority decision circuit, when the memory contents are different between the two brute force memory cells, the memory cells other than the two brute force memory cells. It is determined that the memory content does not suffer from the soft error, the memory cell determined to have not suffered the soft error is selected as the memory cell to be output, and the memory content of the selected memory cell is output. 4. The memory device with a soft error countermeasure function according to claim 2, further comprising a word selector configured. 5. The comparison means is configured to execute the majority comparison on a word-by-word basis when storage contents are output in word units defined by a predetermined bit length from each of the memory cells. The memory device with a soft error countermeasure function according to any one of claims 3 to 4, wherein the memory device has a soft error countermeasure function. 6. The comparing means is configured to execute the majority comparison on a bit-by-bit basis when stored contents are output from each of the memory cells with a predetermined bit length. The memory device with a soft error countermeasure function according to claim 3. 7. Each of the compare means outputs a signal of a logical value H when the storage content of the memory cell that has performed the majority comparison is correct, and the storage content of the memory cell that has performed the majority comparison is Outputting a signal having a logical value L when being incorrect, the word selector means using an output signal from each of the compare means and storage contents output from each of the three or more memory cells, Selecting a memory cell specified by the logical value H as a memory cell having a correct storage content;
5. The storage device according to claim 4, wherein the stored contents indicate output of the stored contents of a correct memory cell.
A memory device with a soft error countermeasure function described in 1. 8. At a timing of writing back to the same address or at a timing controlled from the outside, the storage contents of the memory cells not suffering from the soft error received from the word selector means are subjected to at least the soft error. Updating means for performing a soft error recovery process of re-inputting the data input end of the memory cell having the soft error to rewrite the storage content of the memory cell suffering the soft error to the storage content of the memory cell not suffering the soft error The memory device with a soft error countermeasure function according to any one of claims 1 to 7, comprising: 9. A soft error countermeasure method for judging a soft error of a memory cell and selectively outputting data judged not to have suffered a soft error, wherein the data is stored in at least three or more memory cells. And a majority decision step of performing a majority decision process on the stored contents of each of the three or more memory cells to select data free from a soft error. Countermeasure. 10. The majority decision step, when it is determined that the memory content of any one of the three or more memory cells has suffered a soft error, the remaining memory cells excluding the memory cells are not affected. 10. The soft error countermeasure method according to claim 9, wherein a selection process using a majority decision logic that determines that the storage contents of the memory cells do not suffer from a soft error is executed. 11. The majority decision step includes a compare step which is provided in the same number as the number of the memory cells and performs a majority decision comparison in which two sets of stored contents read from each of the memory cells are compared in a brute force set. The soft error countermeasure method according to claim 10, wherein: 12. The method according to claim 11, wherein the memory cell is a memory cell other than the memory cells set in the brute force group when the memory contents are different between the two brute force memory cells. A word selector that determines that the memory content has not suffered a soft error, selects the memory cell determined to have not suffered the soft error as a memory cell to be output, and outputs the memory content of the selected memory cell. The method according to claim 10, further comprising a step. 13. The comparing step, wherein when the storage contents are output from each of the memory cells in a word unit defined by a predetermined bit length, the majority comparison is performed in a word unit on the storage contents. The soft error countermeasure method according to any one of claims 11 to 12. 14. The comparing step includes the steps of: when storage contents are output with a predetermined bit length from each of the memory cells;
13. The soft error countermeasure method according to claim 11, wherein the stored content is subjected to the majority comparison in bit units. 15. Each of the compare steps outputs a signal of a logical value H when the storage content of the memory cell that has performed the majority comparison is correct, and the storage content of the memory cell that has performed the majority comparison is Outputting a signal of a logical value L if incorrect, the word selector step using an output signal from each of the compare steps and storage contents output from each of the three or more memory cells, Selecting a memory cell specified by the logical value H as a memory cell having a correct storage content;
13. The soft error countermeasure method according to claim 12, wherein the stored contents indicate the output of the stored contents of a correct memory cell. 16. At a timing of writing back to the same address or at a timing controlled from the outside, the storage contents of the memory cells not having suffered the soft error received from the word selector step are subjected to the at least soft error. Update process for performing a soft error recovery process of re-inputting the data input end of the memory cell to rewrite the storage content of the memory cell suffering the soft error to the storage content of the memory cell not suffering the soft error The soft error countermeasure method according to any one of claims 9 to 15, comprising: