JPH05266692A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the reliability of cell data by detecting an error bit at the time of readout of the data and by conducting rewriting on the basis of real data held temporarily. CONSTITUTION:Real data in a memory cell and error correction code data are compared in an error bit detecting circuit of an ECC circuit. When an error bit is detected, data in a data holding part 22 are reset by a reset signal R. Then, an input/output circuit uses an error bit detection signal as a data inversion signal T, the correlation between the data of input/output parts 23 and 24 is inverted by a data inverting part 21, correction of the data is executed on the basis of the data in the data holding part 22 and correct data are rewritten in a memory cell array. Since readout data are corrected and rewritten in this way even when a soft error occurs, relief of the data is enabled and thus the reliability of cell data can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device in which the reliability of cell data is improved and the retention is improved by correcting and rewriting bit erroneous cell data due to a soft error or the like.

In recent years, in a field requiring a semiconductor device having a built-in memory core such as a mainframe, a work station, a personal computer or the like, not only the amount of data to be handled and the speed of data processing have been increased, but also the reliability of the data has been improved. The improvement of sex is also remarkable.

Along with this, the semiconductor device itself including the memory cell array is required to have an increased storage capacity and a high speed data processing. Therefore, at present, the miniaturization of the semiconductor device is further advanced, and the minimum processing size is required. Became the submicron era. Therefore, in the memory portion of the semiconductor device, the problem of soft error due to α rays has become apparent. But,
If the data is not reliable, the read data will be meaningless no matter how large the capacity and the high speed operation is. Therefore, there is a strong demand for improving the reliability of data.

[0004]

2. Description of the Related Art Heretofore, in semiconductor memory devices, the miniaturization of memory elements (cells) has been advanced with the progress of high integration, large capacity, and high speed.

Along with this, bit ghosts (soft errors) due to the incidence of α rays and the like are likely to occur,
Reliability of data retention is becoming an issue. Therefore, in order to improve the data reliability, ECC (Error Correctimg) using Hamming code or horizontal / vertical parity code is used.
Abbreviation for Code or Error Checking Correcting, which means the latter) semiconductor device with a circuit mounted on the chip.

FIG. 15 shows a DRAM (Dynamic Random Acc
FIG. 6 is a configuration diagram in the case where an ECC circuit is incorporated in an ess memory). In the figure, a semiconductor device in which an ECC circuit is mounted on a chip is roughly composed of a memory core section, an ECC circuit section, an input / output control section, and a control section.

The memory core section receives signals from the memory cell array 1 having a plurality of word lines and a plurality of bit lines and the row address buffer 2 and outputs signals to the word lines to select cells in the row direction of the memory cells. It includes a row decoder 3 for outputting, a column gate 5 for receiving the output of the column decoder 4 to select a bit line, and a sense amplifier 6 for inputting / outputting data of the bit line selected by the column gate 5.

The ECC circuit unit detects an error portion (error bit) of data from the data (actual data and code code for error bit correction) output via the sense amplifier I / O circuit 6 during the data read operation. An error bit detection circuit 7, and an error bit correction circuit 8 that corrects the error bit according to the error bit correction code output by the error bit detection circuit 7 and outputs correct data when the output data includes the error bit. , An error code generation circuit 9 for generating an error correction code from input data when writing data
Consists of.

Further, the input / output control section forcibly operates the sense amplifier 6 via the column gate 5 and controls the exchange of data with the input control circuit (write buffer) 10 for rewriting cell data. And an input / output control circuit 11.

Further, the control unit controls the write enable signal W
The control signal generation circuit 12 generates each mode control signal of the DRAM from the E #, the row address strobe signal RAS #, and the column address strobe signal CAS #, and generates various timing signals.

At the time of writing data, the data input through the input / output control circuit 10 is combined with the error correction code data generated by the error code generation circuit 9.
It is stored in a predetermined cell whose address is selected by the sense amplifier I / O circuit 6.

At the time of reading data, the sense amplifier 6
Compares the actual data stored in a predetermined cell selected by address selection with the error correction code data, generates an error bit correction code when an error bit of the actual data is detected, and the error bit correction circuit 8 , The actual data is corrected according to the bit correction code and is output via the input / output control circuit 10.

As described above, in order to improve the reliability against the soft error in the semiconductor memory device, the ECC circuit may be built in and used as in the conventional example. However, the soft error does not always occur only once in time, and may occur repeatedly twice or three times.

However, in the prior art, the second and third soft errors could only be viewed as the accumulation of defective bits. Therefore, in order to deal with the soft error twice or three times, the number of detected defective bits may be increased, that is, the data length of the error correction code may be increased, but this also has its own limit and the cell Cause an increase.

In order to solve the above problems, the data in the memory cell array 1 is read once before the second and third soft errors occur, and the read data is corrected by the ECC circuit to obtain correct data. The memory cell array 1 may be rewritten.

In general, a plurality of electrically continuous bits do not blunt due to a soft error, and the second and third soft errors occur in adjacent bits in an expected value which is considerably long in time. , It is only necessary to correct the cell data before the third soft error occurs, and when the first soft error occurs, it is not necessary to correct the data (or bit) immediately. At the time of correction, correct data may be rewritten in the cell. In addition, the semiconductor memory device is a DRAM
If it is, the cell data can be corrected at the time of refreshing.

When such a method is attempted by improving the current ECC circuit, the signal flow of the error bit correction circuit 8 is unidirectional, so that not only the number of signal lines increases but also
When data is returned to the cell and rewritten, the error bit correction code changes.

[0018]

As described above, in the conventional semiconductor memory device, (1) a method of increasing the data length of the error correction code in order to deal with the soft error twice or three times is provided. Has a limit and causes an increase in cells,
(2) The method of correcting the read data by the ECC circuit and rewriting the data in the memory cell array has a problem that the number of signal lines is increased and the error bit correction code is changed at the time of rewriting.

The present invention solves the above-mentioned problems.
It is an object of the present invention to provide a semiconductor memory device in which reliability of cell data is improved by correcting cell data having bit errors due to a soft error and rewriting the data.

[0020]

In order to solve the above problems, the semiconductor memory device of the first feature of the present invention is shown in FIG.
As shown in (1), the first input / output unit 23 formed of complementary input / output signal lines and the second input / output unit 24 formed of signal lines corresponding to the first input / output unit 23 in a one-to-one correspondence. And a data inverting section 21 for inverting the correspondence relationship between the data of the first input / output section 23 and the second input / output section 24 by an inversion signal T, and at least one pair of complementary input / output signal lines. And a data holding unit for holding the input / output data and resetting the data held in the data holding unit 22 by the reset signal R and outputting the held data to the data inverting unit 21 again. The input / output unit 23, the second input / output unit 24, and the input / output unit 25 flow in both directions, and the first input / output of the data inverting unit 21 is provided. Either the unit 23 or the second input / output unit 24 is Constituting a output circuit 13 connected to the output unit 25 of the data holding unit 22.

The semiconductor memory device of the second feature of the present invention is
The semiconductor memory device according to claim 1, wherein FIG.
3, the input / output circuit 13 includes one data holding unit 22 and a plurality of independent data inverting units 21.
-1, 11-2 are included and configured.

The semiconductor memory device according to the third aspect of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the input / output circuit 13 is used as a write buffer as shown in FIGS. Then, the input / output circuit 13 resets the data in the data holding unit 22 by the reset signal R, holds the cell data read by the sense amplifier through the data inverting unit 21, and inverts the held data. In response to the signal T, the data inverting unit 21 outputs the data to the cell without inverting or inverting the data and rewriting the cell data.

The semiconductor memory device of the fourth feature of the present invention is the semiconductor memory device according to claim 1 or 2, wherein the input / output circuit 13 is a write buffer and a sense circuit as shown in FIGS. Used as an amplifier, the input / output circuit 13 resets the data in the data holding unit 22 by a reset signal R, and then the data inverting unit 21.
The bit line output is amplified through the holding circuit and held, and the held data is output to the cell by the data inversion signal T without inverting or inverting the data in the data inverting unit 21, and the cell data is rewritten.

Furthermore, the semiconductor memory device of the fifth feature of the present invention is the semiconductor memory device according to claim 3 or 4, wherein as shown in FIG. 4, at least the memory cell array for storing the actual data and the error correction code data. 1, an error bit detection circuit 7 for detecting an error bit by comparing the actual data and the error correction code data, and an input / output circuit 13 according to claim 3 or 4, and the memory cell array 1 The error bit detection circuit 7 outputs an error bit detection signal when the data is read, and the input / output circuit 1
3 indicates the error bit detection signal to the data inversion signal T
Then, the data is inverted by the data inverting section 21 to correct the data, and correct data is rewritten in the memory cell array 1.

[0025]

In the semiconductor memory device of the present invention, as shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, in order to rewrite the correct data in the memory cell array 1, the read data is temporarily held and the data is corrected. The signal flow of the ECC circuit unit is configured to be bidirectional.

That is, at least the memory cell array 1 for storing the actual data and the error correction code data, the error bit detection circuit 7 for detecting an error bit by comparing the actual data and the error correction code data, and the data in the data holding section 22 are stored. After being reset by the reset signal R, the data inversion unit 2
An input / output circuit 1 for rewriting cell data by holding the data via 1 and outputting the held data to the cell by the data inversion signal T without inverting or inverting the data by the data inversion unit 21.
3 is built into the semiconductor memory device, and the input / output circuit 13 is
Using the error bit detection signal as the data inversion signal T, the data inversion unit 21 inverts the data to correct the data and rewrite the correct data in the memory cell array 1.

Therefore, even if a soft error occurs twice or three times, the read data is corrected by the ECC circuit,
Since data is rewritten in the memory cell array, data can be saved and the reliability of cell data can be improved. Since the signal flow of the ECC circuit section for data correction is bidirectional, there is no increase in the number of signal lines and no change in the error bit correction code during rewriting.

[0028]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 4 shows a configuration diagram of a semiconductor memory device (DRAM) according to an embodiment of the present invention. In FIG.
The same symbols are attached to the portions that overlap with (conventional example).

In the figure, the semiconductor memory device of this embodiment is roughly composed of a memory core portion, a column I / O circuit 13,
It is composed of an ECC circuit section, an input / output control section, and a control section. In the following description, a signal followed by # after the signal name is a negative logic signal.

The memory core section comprises a memory cell array 1, a row address buffer 2, a row decoder 3, a column gate 5 and a sense amplifier 6. Memory cell array 1
As shown in FIG. 5, a plurality of word lines X ₁ to X _n and a plurality of bit lines _{BL 1, BL 1 # ~BL l} , it has a configuration including a BL _l #.

As shown in FIG. 6A, the row address buffer 2 latches the row address RADR by the address input ADDR and the row address strobe signal RAS # and outputs it to the row decoder 3.

As shown in FIG. 6B, the row decoder 3 selects _one of the word lines X _{1 to} X _n according to the row address RADR and the mode control signal φ ₁ .
As shown in FIGS. 7A and 7B, the column decoder 4 includes a column address buffer for latching the column address CADR by the address input ADDR and the column address strobe signal CAS #, and a column address CAD.
A column predecoder that selects _one of the plurality of column gate input lines Y _{1 to} Y _n in response to R, the column address strobe signal CAS #, the column predecoder, and the mode control signal φ ₁ .

As shown in FIG. 8, the column gate 5 receives the column gate input lines Y _{1 to} Y _n and outputs the sense amplifier output lines BL ′ ₁ , BL ₁ ′ # to BL _l ′, BL _l ′ #. 1
Select a book.

As shown in FIG. 9, the sense amplifier 6 connects the bit line BL ₁ , to the sense amplifier output lines BL ' ₁ , BL ₁ '# to BL _l ', BL _l '# selected by the column gate selection signal. BL ₁ # ~BL _l, outputs the signal data of the BL _l #.

The ECC circuit section includes an error bit detection circuit 7, an error bit correction circuit 8 and an error code generation circuit 9.
Consists of. The error bit detection circuit 7, as shown in (1) and (2) of FIG. 10, outputs the data x output via the sense amplifier 6 and the column gate 5 during the data read operation.
_{1, x 1 # ~x 8,} x 8 # and _{p 1, p 1 # ~p 4} , p 4
# (Actual data and error bit correction code)
Data x ₁ , x ₁ # to x ₈ , x ₈ # and p ₁ , p ₁ # to p
₄ , an error part (error bit) of the data is detected from the signals B _{1 to} B ₁₂ which are latch data of p ₄ #, and error bit correction signals C _{1 to} C ₁₂ are generated and output to the error bit correction circuit 8. ..

The error bit correction circuit 8 outputs the error bit correction code output from the error bit detection circuit 7 when the output data B _{1 to} B ₁₂ include error bits as shown in FIG. 11 (1). The error bit is corrected according to C _{1 to} C ₁₂ , and correct data D _{o1 to} D _o8 are output.

As shown in FIG. 11 (2), the error code generation circuit 9 inputs the input data D _{I1 to} D _I8 when writing data.
Error correction codes D _{I9 to} D _I12 are generated from The input / output control unit includes an input control circuit (write buffer) 10 and an input / output control circuit 11.

Input control circuit (write buffer)
As shown in FIG. 12 (1), 10 forcibly operates the sense amplifier 6 via the column gate 5, and further rewrites cell data.

The input / output control circuit 11 is shown in FIG.
As shown in (2), the exchange of data with the outside is controlled, and during the write operation, the input data D _{1 to} D ₈ are transferred to D _I1 to
Transmitted to the error code generating circuit 9 and the input control circuit 9 as D _I8, during the read operation the output data D _o1 to D _o8
Is transmitted to the data buses D _{1 to} D ₈ .

Further, the control section, as shown in FIG. 13, has a write enable signal WE #, a row address strobe signal RAS #, and a column address strobe signal CAS.
From # to each mode control signal φ ₁ , φ ₂ , φ ₃ ,
The control signal generating circuit 12 generates φ ₄ and generates various timing signals.

Next, the column I / O circuit 13 has a structure as shown in FIG. 14, and resets the data in the data holding section 22 by the reset signal φ ₁ and then outputs the data x output via the column gate 5. _{1, x 1 # ~x 8,} x 8 # and _{p 1, p 1 # ~p 4} , p 4 and #, and held in the data holding unit 22 via the data inversion section 21, the held data is data inversion Instead, the data is output as the signals B _{1 to} B ₁₂ , and the held data is corrected by the data inverting section 21 by inverting or not inverting the data according to the error bit correction signals C _{1 to} C ₁₂ , and the data x ₁ and x ₁ are corrected again. # ~x _8, x ₈ # and p _1, p ₁ # output as ~p _4, p ₄ #, rewrite the cell data.

When writing data, the column I /
The O circuit 13 has an input control circuit 10 and an output B.₁~ B
₁₂Data x₁, X₁# ~ X₈, X₈# And p₁, P₁#
~ P _Four, P_FourTransmit as # as the data is not inverted
It is only.

As described above, in this embodiment, when the data is read from the memory cell array 1, the ECC circuit section detects an error bit, the column I / O circuit 13 corrects the read data, and outputs correct data. , Correct data is rewritten in the memory cell array 1. Therefore, even if a soft error occurs next time, the ECC circuit section can relieve the data, which largely contributes to the improvement of the reliability of the cell data and the improvement of the retention (data retention characteristic).

In this embodiment, a DRAM is used as an example of the semiconductor memory device, but SRAM (Static R
AM) Flash EPROM (Erasable Programmable Re)
It is also applicable to ad only memory).

Further, the input / output circuit 13 of the present embodiment can be used in the ECC circuit because it holds the output data from the cell and then inverts or non-inverts this data and rewrites it in the cell. Like image memory,
Even in a semiconductor device that requires an operation of reading or writing by inverting all data by 0/1, the operation can be easily performed by a change in address and one control signal.

[0046]

As described above, according to the present invention,
A memory cell array that stores at least actual data and error correction code data, and an error bit detection circuit that detects an error bit by comparing actual data and error correction code data,
After the data in the data holding unit is reset by the reset signal R, it is held via the data inverting unit, and the held data is output to the cell by the data inverting signal without inverting or inverting the data in the data inverting unit. And an input / output circuit for rewriting the data, the input / output circuit uses the error bit detection signal as a data inversion signal to invert the data in the data inversion section to correct the data and to obtain correct data in the memory cell array. Since it is decided to rewrite the data, even if a soft error occurs twice or three times, the data can be relieved, the reliability of the cell data is improved, and the retention (data retention characteristic) is improved.
It is possible to provide a semiconductor memory device having improved characteristics.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input / output circuit with a data inversion function of the present invention, FIG. 1 (1) is an explanatory view of the principle of the present invention (claim 1), and FIG. 1 (2) is an input / output with a data inversion function. It is a circuit diagram of a circuit.

FIG. 2 is a circuit diagram of an input / output circuit with a data inversion function of the present invention, FIG. 2 (1) is an explanatory view of the principle of the present invention (claim 2), and FIG. 2 (2) is an input / output with a data inversion function. It is a circuit diagram of a circuit.

FIG. 3 is a diagram for explaining the principle of the present invention (claims 3 and 4).

FIG. 4 illustrates a semiconductor memory device (DR according to an embodiment of the present invention.
It is a block diagram of (AM).

FIG. 5 is a circuit diagram of a memory cell array according to an embodiment.

FIG. 6 (1) is a circuit diagram of a row address buffer of the embodiment, and FIG. 6 (2) is a circuit diagram of a row decoder of the embodiment.

FIG. 7 (1) is a circuit diagram of a column predecoder of the embodiment, and FIG. 7 (2) is a circuit diagram of a column address buffer of the embodiment.

FIG. 8 is a circuit diagram of a column gate of the embodiment.

FIG. 9 is a circuit diagram of a sense amplifier I / O gate according to an embodiment.

FIG. 10 is a circuit diagram of an error bit detection circuit according to an embodiment.

11 (1) is a circuit diagram of an error bit correction circuit of the embodiment, and FIG. 11 (2) is a circuit diagram of an error code generation circuit of the embodiment.

FIG. 12 (1) is a circuit diagram of an input control circuit (write buffer) of the embodiment, and FIG. 12 (2) is a circuit diagram of an input / output control circuit of the embodiment.

FIG. 13 is a circuit diagram of a control signal generation circuit according to an embodiment.

FIG. 14 is a circuit diagram of a column I / O circuit according to an embodiment.

FIG. 15 is a configuration diagram of a conventional semiconductor memory device (DRAM).

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Row address buffer 3 ... Row decoder 4 ... Column decoder 5 ... Column gate 6 ... Sense amplifier 7 ... Error bit detection circuit 8 ... Error bit correction circuit 9 ... Error code generation circuit 10 ... Input control circuit (write) Buffer) 11 ... I / O control circuit 12 ... Control signal generating circuit 13 ... Column I / O circuit (input / output circuit) 21, 21, 21-21 ... Data inverting section 22 ... Data holding section 23 ... First input output unit 24: second input-output unit 25 ... input portion T ... inverted signal R ... reset signal X ₁ to X _n ... word lines _{BL 1, BL 1 # ~BL l} , BL l # ... bit lines ADDR ... address Input RADR ... Row address CADR ... Column address WE # ... Write enable signal RAS # ... Row address strobe signal CAS # ... Ram address strobe signal _{φ 1, φ 2, φ 3} , φ 4 ... mode control signal Y ₁ to Y _n ... column gate input line _{BL '1, BL 1'#} ~BL l ', BL l'# ... sense amplifier output line _{x 1, x 1 # ~x 8} , x 8 # ... column gate 5 outputs data (actual _{data) p 1, p 1 # ~p} 4, p 4 # ... column gate 5 outputs data (code code for error correction bits ) B _{1 to} B ₁₂ ... Latch data signal C _{1 to} C ₁₂ ... Error bit correction signal D _{o1 to} D _o8 ... Error bit correction circuit 8 output data D _{I1 to} D _I8 ... Input data D _{I9 to} D _I12 ... Error correction code D _{1 to} D ₈ ... Input / output data

Claims (5)

[Claims] 1. A first input / output section (23) comprising complementary input / output signal lines, and a one-to-one correspondence with the first input / output section (23).
And a second input / output unit (24) composed of a corresponding signal line, and the first input / output unit (2) is provided by an inverted signal (T).
3) and a data inverting part (21) for inverting the correspondence between the data of the second input / output part (24), and an input / output part (25) comprising at least one pair of complementary input / output signal lines, After the data held in the data holding unit (22) is reset by the reset signal (R), the input / output data is held and the held data is output to the data inverting unit (21) again ( 22), and the first input / output unit (23) and the second input / output unit (2)
4) and the signal flow of the input / output unit (25) is bidirectional, and is either the first input / output unit (23) or the second input / output unit (24) of the data inverting unit (21). One is a semiconductor memory device having an input / output circuit (13) connected to the input / output unit (25) of the data holding unit (22). 2. The input / output circuit (13) has one data holding section (22) and a plurality of independent data inverting sections (21-1, 21-2). The semiconductor memory device according to claim 1. 3. The input / output circuit (13) is used as a write buffer, and the input / output circuit (13) includes the data holding unit (22).
After resetting the data of with the reset signal (R),
The cell data read by the sense amplifier is held via the data inverting section (21), and the held data is output to the cell by the data inverting signal (T) without inverting or inverting the data in the data inverting section (21). 3. The semiconductor memory device according to claim 1, wherein the cell data is rewritten. 4. The input / output circuit (13) is used as a write buffer and a sense amplifier, and the input / output circuit (13) includes the data holding unit (22).
After resetting the data of with the reset signal (R),
The bit line output is amplified through the data inverting unit (21) and held, and the held data is stored in the cell by the data inverting signal (T) without inverting or inverting the data in the data inverting unit (21). 3. The semiconductor memory device according to claim 1, wherein the cell data is rewritten to the cell data and rewritten. 5. A memory cell array (1) for storing at least real data and error correction code data, and an error bit detection circuit (7) for detecting error bits by comparing the real data and error correction code data. 3. The input / output circuit (13) according to 3 or 4, wherein the error bit detection circuit (7) outputs an error bit detection signal when reading data from the memory cell array (1). (13) uses the error bit detection signal as the data inversion signal (T), and outputs the data inversion unit (2).
5. The semiconductor memory device according to claim 3, wherein the data is corrected by inverting the data in 1), and correct data is rewritten in the memory cell array (1).