JPH01273154A - Storage device with ecc circuit - Google Patents

Abstract

PURPOSE:To execute at a high speed a read operation for an area which does not necessitate an ECC (Error Correct Code) check by providing an ECC check enable bit storage part and designating whether it is necessary to execute the ECC check or not at every prescribed area unit of a data storage part. CONSTITUTION:The title device is provided with an ECC check enable bit storage part 4 for storing a bit for designating whether an ECC check is to be executed or not at every prescribed area unit of a data storage part 2. In this state, by the bit for designating whether a check of an ECC error is necessary or unnecessary which has been given at a prescribed area unit of a data storage part 2, an area to which the ECC error check is not required is designated. In such a way, the time for the ECC check at the time of read of this area becomes unnecessary, and the read operation can be executed at a higher speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is based on E CC (Error Corrae
The present invention relates to a storage device with an ECC circuit that is equipped with an ECC circuit that detects errors in a memory array.

[Conventional technology]

FIG. 3 shows [Interface J NQ87. P245-
This is a block diagram of a storage device including a conventional Ecc check circuit shown in P250 (Publisher: CQ Publishing, Publication date: August 1984). In addition to the
A data storage section 3 is provided in the memory array 1 in which various data are written, and a check pit storage section 5 stores check pits added to each data stored in the data storage section 2. Single bit errors and double bit errors are detected based on the check pit information in the check pit storage unit 3 for the data in the storage unit 2, and a signal SEP (single bit error flag) and a signal DEF (double bit error flag) are detected, respectively. ); 6 is a data storage unit 2 in the memory array 1; Controls read and write operations of data in the check pit storage unit 3, and provides address data and signal RAS (Low Address 5trobe)
, signal CAS (Column Address 5
, signal WE (Write E nabl)
e) to the memory array 1.

Next, the operation will be explained with reference to the timing chart shown in FIG. When writing data, first, the memory control section 6 sets the signal WE to "L", and the ECC error detection section 5 generates a check bit for the confirmed data. Furthermore, the memory control unit 6 lowers the signal RAS and the signal CASL to "L" at the time when the row address (upper address) and column address (lower address) generated on the address lines in a time-division manner are determined.
”, the data storage unit 2 and check bit storage unit 3 input the row address at the timing when the signal RASL becomes “L7+”, and input the row address and input the data at the timing when the signal CASL becomes “LH”. Alternatively, write check pits.

On the other hand, during reading, the memory control unit 6 outputs the signal WE as “
With this operation, the signal RAS and the signal CAS are set to "L" at the same timing as the writing time while the data is kept at "H", and data or check pits are output from the data storage section 2 and the check pit storage section 3. The ECC error detection section 5 inputs the data read out from the data storage section 2 and the check pit, and detects 1-bit errors and 2-bit errors.If there is a 1-bit error,
The signal SEP is set to "L", and when a 2-bit error occurs, the signal DEF is set to "L".

[Problem to be solved by the invention]

Since the conventional storage device with an ECC circuit is configured as described above, 1-bit errors and 2-bit errors are detected during read recycling for the entire area of the data storage section 2, and therefore, an ECC check is especially necessary. Even in the case of reading an area that does not contain data, it takes time to detect a 1-bit error or a 2-bit error, which causes a problem in that the processing speed using such an area decreases.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a storage device with an ECC circuit that can increase the processing speed of ECC checks by increasing the reading speed of areas where ECC checks are not performed. shall be.

[Means for Solving the Problems] A storage device with an ECC circuit according to the present invention includes an ECC check enable bit storage section that stores a bit specifying whether or not to perform an ECC check for each predetermined area unit of a data storage section. By changing the storage unit control method for each predetermined area between the case where the ECC check is performed and the case where the ECC check is not performed, the reading speed for the area where the ECC check is not performed can be increased.

[Effect]

In the storage device with an ECC circuit according to the present invention, the ECC check enable bit is stored in the ECC check enable bit storage section. A bit that specifies whether ECC error checking is necessary or unnecessary is assigned to each predetermined area of the data storage unit to specify an area that does not require ECC error checking, and the time required for ECC checking when reading this area. This eliminates the need for faster read operations.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. In FIG. 1, the same parts as in FIG. An ECC that stores a bit that specifies whether or not to perform an ECC check for each unit of a certain area of the array.
This is a check enable bit storage unit. therefore,
An ECC check enable bit is written into the ECC check enable bit storage section 4 from the memory control section 6. Further, FIG. 2 is a timing diagram showing a read operation of the circuit of FIG. 1.

Next, the operation will be explained. The ECC check enable bit storage section 4 is assigned an address for storing 1-bit ECC check enable information (that is, an ECC check enable bit) for each fixed area unit of the memory array of the data storage section 2. There is. This allocation can be done, for example, if the capacity of the data storage unit 2 is LM (2
”) bytes, with 20-bit addresses A, ~A1 .
A storage device that addresses one piece of data in 1x
(21@) Taking as an example the case where the above ECC check enable information is attached in byte units, in this case, the above ECC check enable information will be attached to a total of 216 areas, and the data Storage part 2
EC the upper 10 bits (A1° to A1.) of the address of
By applying the ECC check enable bit to the C check enable bit storage unit 4, it is possible to obtain the ECC check enable bit for the entire area of the corresponding memory array. That is, such ECC check enable information is set in advance to the entire area of the ECC check enable bit storage unit 4, for example, by setting it to "0"("L") to perform the ECC check with "1"("H"). Write it as not performing ECC check.

FIG. 2 shows the timing of a read operation with and without ECC checking. A DRAM is used for the data storage section 2 and the check bit storage section 3, and a static RAM (SRAM) or the like is used for the ECC check enable bit storage section 4, which can read data faster than DRAM. However, if you want to perform an ECC check, do so on a read operation.

The ECC check enable bit storage unit 4 stores the upper addresses A1° to A1. is given, the ECC of the corresponding area before the data and check bits are determined.
The check enable bit is determined as 81111 (“H”). This information is input to the memory control unit 6 and
It waits until the CC check is completed, that is, until the signals SEP and DEF are confirmed, and if there is no error, the read operation is ended. In other words, if the ECC check pit is “1” (“H”), the conventional FCC
The operation is similar to that of a memory device with circuit.

On the other hand, if the ECC check is not performed, before the data and check pits are determined during the read operation,
The ECC check enable bit of the corresponding area is “0”
” (“L”). Based on this information, the memory control unit 6 finishes the read operation after the data is fixed without waiting for the end of the ECC check.

Incidentally, in the above embodiment, the ECC check enable bit storage section is constituted by a memory element.

It may also be specified by hardware such as a switch.

Furthermore, the ECC check enable bit is not just one bit, but a plurality of bits may be used to improve reliability and provide redundancy.

〔Effect of the invention〕

As described above, according to the present invention, by providing the ECC check enable bit storage section in the storage device with an FCC circuit, the ECC check enable bit storage section is provided.
Since I configured it so that I can specify whether or not to execute the check,
For each area inside the data storage unit, you can specify areas where ECC checking is performed and areas where ECC checking is not performed.
This has the effect that reading operations in areas that do not require CC checking can be performed faster.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a storage device with an ECC circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the circuit in FIG. 1, and FIG. 3 is a conventional storage device with an FCC circuit. FIG. 4 is a timing diagram showing the operation of the circuit of FIG. 3. 2... Data storage section, 3... Check pit storage section, 4... ECC check enable bit storage section, 5
...ECC error detection section. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent Applicant: Mitsubishi Electric Corporation r ------------11--Co Figure 2 r-----= ------11--1 Figure 4 Blind Screen t Operation WEゝH'I EF

Claims (1)

[Claims] a data storage unit; a check bit storage unit that stores check bits added to each data stored in the data storage unit; and a check bit storage unit that detects an error in a single bit or multiple bits of data read from the data storage unit. E.C.C.
The storage device with an ECC circuit includes an ECC check enable bit storage section that stores a bit specifying whether or not to perform an ECC check for each predetermined area unit of the data storage section, Specify whether ECC check is necessary or not for each
A storage device with an ECC circuit, characterized in that it is possible to speed up read operations in areas where no checking is performed.