JPS63187335A - Data selecting method - Google Patents

Abstract

PURPOSE:To execute a selection by a memory device which has decreased 1 bit per 1 word, by constituting each word of the memory device of 3 bits, and assigning three kinds of values in which a hamming distance is separated by >=2 among eight kinds of values which can be expressed by 3 bits, to an initial state, an existence state of a data group 1, and an existence state of a data group 2, respectively. CONSTITUTION:A memory device storing the existence of data of both data groups is collected to one, and its 1 word is constituted of 3 bits. Subsequently, among eight kinds of values which can be expressed by 3 bits, three kinds of values in which a hamming distance is separated by >=2 are selected, and are assigned to an initial state, an existence state of a data group 1, and an existence state of a data group 2, respectively. In such a way, a memory which is constituted of total 4 bits per 1 word up to now can be decreased to 3 bits per 1 word, while keeping the same effect.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a data selection method for selecting only data whose data contents match each other from two data groups.

(Prior Art) In the field of data processing, there is often a need to extract and combine data whose data contents match each other from two data groups. In this case, if the amount of data in each data group is large, it will take a long time to combine directly, so data selection is performed to shorten the combining time by removing data that has no possibility of being combined from each data group in advance. The following operations are used.

Figure 5 is a diagram explaining the principle of conventional data sorting operation.
1 and 2 are data groups, 3 is a hash circuit having a predetermined hash function, 4 and 5 are memory devices whose address spaces are hash values, and 6 and 7 are selected data groups.

The operation begins by writing all the words in the memory devices 4 and 5 as it Oj
After setting j, each data content of the data group l is converted into a hash value by the hash circuit 3, and "'1" is set in the corresponding word of the memory device 5 corresponding to the value. This operation is called operation 10.

When operation 10 is completed, the hash circuit 3 converts each data content of the data group 2 into a hash value 1, and the corresponding word in the memory device 5 corresponding to that value is referred to, and the value is "1".
'', the data matches data group 1, and that data is selected to obtain data group 7, and tt I II is set in the corresponding word of the memory device 4 corresponding to the hash value. This operation is called operation 11.

When operation 11 is completed, each data content of data group 1 is converted into a hash value again by the hash circuit 3, and the corresponding word in the memory device 4 corresponding to that value is referred to, and the value is /(
11g, the data matches data group 2, and that data is selected and data group 6 is selected.
get.

This operation is called operation I2.

In FIG. 5, for example, if data group 1 is "ABDDFG" and data group 2 is "AACDEFH", selected data groups 6 and 7 are "ADDF" and "AADFF".
This shows that it is possible to obtain

FIG. 6 is a time chart of operations 10.11.12 in FIG.

In the above explanation, one word of the memory devices 4 and 5 is
Logically it is 1 bit, but in order to deal with 1-bit failures in memory, it is often known that the memory is made up of 2 bits, with the 1st bit being the data bit and the 2nd bit being the parity bit. Measures will be taken to deal with memory device failures.

In this case, KI OI II becomes logical ego”, t
L 10 jl is made to correspond to logical "1", and if II OOII and PA 11''' other than these are read, it is determined that a failure has occurred in the memory device and predetermined failure processing is performed.

Therefore, the total number of bits per word is 4 bits in two memory devices.

The configurations of the memory devices 4, 5 in this method are the same.

FIG. 7 shows an example of the configuration of a conventional memory device, where 91 is an address register, 92 is a write register, 93 is a read register, 94 is a control circuit, and 95 is a 2-bit memory.

In order to accurately select matching data in data groups 1 and 2 using the above method, the number of words in the memory device 4.5 must be 5 times to 1 times the maximum allowable number of data in data groups 1 and 2.
0x is required.

Moreover, since the above method is applied when the maximum permissible number of data in a data group 1゜2 is extremely large, the fact that the parity pits have a total of 2 bits has the disadvantage of greatly increasing the scale of the device. ing.

(Object of the invention) The object of the present invention is to maintain the same sorting accuracy as the conventional method,
Another object of the present invention is to provide a method for selecting a memory device with one bit less per word.

(Structure of the Invention) (Characteristics of the Invention and Differences between the Prior Art) The present invention combines memory devices that record the existence of data of both data groups into one, and makes one word of the memory device consist of 3 bits. The most important feature is that out of the eight values that can be expressed, three values with a Hamming distance of 2 or more are selected and assigned to the initial state, the existence state of data group 1, and the existence state of data group 2, respectively. do.

(Example) FIG. 1 is a diagram explaining the principle of an embodiment of the data selection method of the present invention, in which 1 and 2 are data groups, 8 is a hash circuit having a predetermined hash function, and 9 is a hash value. A memory device serving as an address space, 6.7 is a selected data group.

The memory device 9 has a 3-bit configuration, as will be described in one embodiment later.

The operation begins by putting all words in the memory device 9 into the "initial state" (
For example, '101'), each data content of data group 1 is converted into a hash value by hash circuit 8, and the corresponding word of memory device 9 corresponding to that value is written as ``existence state of data group 1''. (For example, “110”)
Set. This operation is called operation 13.

When operation 13 is completed, the hash circuit 8 converts each data content of the data group 2 into a hash value, and the corresponding word in the memory device 9 corresponding to that value is referred to, and the content is "
110" or is already "011", (1) It is assumed that data matching data group 1 exists, and that data is selected to obtain data group 7.

■ At the same time, the corresponding word of the memory device 4 corresponding to the hash value is written as the “existence state of data group 2” (for example, “011
”).

This operation is called operation 14.

When operation 14 is completed, the data content of data group 1 is again converted into a hash value by the hash circuit 8, and the corresponding word in the memory device 9 corresponding to that value is referred to, and if the content is "011", , the data matches data group 2, and that data is selected to obtain data group 6.

This operation is called operation 15.

In Figure 1, data group 1 is set to IIABDD as in Figure 5.
FG”, data group 2 is “AACDEFFH”, the selected data group 6.7 is “ADDF”, “A
This shows that "ADFF" can be obtained.

FIG. 2 is a time chart of operations 13, 14, and 15 in FIG.

FIG. 3 shows one embodiment of the memory device 9. As shown in FIG.

In the figure, 90 is a memory with 1 word and 3 bits;
91 is an address register of a memory 90 for setting the hash value output from the hash circuit 8; 92 is an address register of the memory 9;
A write register 93 writes a predetermined value to 0, a read register 93 for the memory 90, and a control circuit 94 for overall control and for determining the result of reading the memory.

FIG. 4 is an explanatory diagram of possible values of one word of the memory 90 and their corresponding states in this embodiment, where FIG. 4(a) is the value of the memory and FIG. 4(b) is the corresponding state. Indicates the state of

“101”, “1], O”, “011” in this example
” is an example of a set of values having a Hamming distance of 2 from each other.

As shown in the figure, the significant states "101", "1"
Anything other than ``10'' and ``011'' is considered to be a failure state, and it is possible to detect a 1-bit memory failure or a 3-bit burst failure (fixed at ``000'' and ``111'').

The present invention is effective regardless of the configuration of the hash circuit 8.

(Effects of the invention) In the conventional method, the memory was 4 bits in total per word, but in the method of the present invention, while maintaining the same effect,
It can be reduced to 3 bits per word.

Assuming that the maximum allowable number of data groups is 100,000, the reduction of 1 bit per word is 500,000 to 1,000,000 bits,
That is, the reduction effect is 61 kilobytes to 122 kilobytes.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of one embodiment of the data selection method of the present invention, FIG. 2 is a time chart of operations 13 to 15 in FIG. 1, and FIG. 3 is an implementation of the memory device 9 in FIG. 1. For example, FIG. 4 is an explanatory diagram of the possible values of one word of the memory 90 and the corresponding states, FIG. 5 is an explanatory diagram of the principle of the conventional data sorting operation method, and FIG. 6 is the operation 10 of FIG. The time chart of .11 and 12, FIG. 7, is an example of the configuration of a memory device using the conventional method. 1.2... Data group, 3.8... Hash circuit, 4.5.9... Memory device with hash value as address space, 6.7... Selected data group, 90.・Memory of 1 word 3 bits 1 ~ configuration, old ・
...Address register, 92...Write register, 93...Read register, 94...Control circuit. Figure 3 92 S public register 93 S female cashier register Figure 4

Claims (1)

[Claims] In order to select only data whose data contents match each other from two data groups, a hash circuit and a memory device whose address space is the hash value output from the hash circuit are provided. A hash value is calculated for each data in group 1, the existence state of data group 1 is recorded in the corresponding word of the memory device corresponding to each hash value, and then a hash value is calculated for each data in data group 2 using the same hash circuit. If the corresponding word in the memory exists, it is assumed that the data in data group 2 matches any data in data group 1 and is selected, and data group 2 is stored in the memory device.
The existence state of data group 1 is recorded, and data group 1 is hashed again using the same hash circuit, and the corresponding word is added to data group 2.
In this data sorting method, each word of the memory device has a 3-bit configuration, and eight types of data that can be expressed with 3 bits are selected. A data selection method characterized in that three types of values separated by a Hamming distance of two or more are assigned to an initial state, an existence state of a data group 1, and an existence state of a data group 2, respectively.