JPS58118097A - Memory device - Google Patents

Abstract

PURPOSE:To reduce the number of memory elements relatively and improve the utilizating efficiency of the memory element, by forming and writing check bits in data width unit by an error correction detecting means, when writing access data in a storing means. CONSTITUTION:When 8-bit data are written, a write signal is first transmitted to an ECC block circuit 2' from the outside, and then, data stored in addresses assigned by addresses A0-An-1 out of the whole addresses A0-An are read out based on the write signal, and inputted into the ECC block circuit 2'. At the ECC block circuit 2', the 8-bit write data are rewritten against the 8 bits at one side assigned by, for example, ''0'' of the lowest bit An of the whole addresses A0-An out of the inputted 16-bit data. Then, a check bit of 6 bits to the 16-bit data is determined at the ECC block circuit 2', and the check bit is written in an assigned address of a memory 1'.

Description

[Detailed description of the invention] (1) Field of technology The present invention relates to a memory device.

In particular, in a memory device that uses check bits to detect and correct errors between stored data and its read data, increase the efficiency of memory element usage by relatively reducing the number of memory elements for check bits. The present invention relates to a memory device having such a structure.

(2) Background of the Technology Many memory devices capable of writing and reading data are used in data processing devices. In these memory devices, unless written data and read data match, subsequent data processing becomes inaccurate. By the way, memory devices store data made up of bits, and these bits take a value of ``0'' or ``1.''

If even one of these bits is inverted due to the influence of the d-line, for example, an error will occur in the data. In particular, recent memory devices have high storage densities, so they are easily affected by the alpha rays. Therefore, a parity check method is used in which a 1-bit check bit is added to the data so that it can be checked if there is an error between the data stored in the memory device and the read data. However, although Tonoku Integrity Check can check for 1-bit errors,
Unable to check for errors in even number of bits. Furthermore, it does not have a function to correct the value of error bits. Therefore, a 5-bit check bit is added to the 8-bit data to perform the above-mentioned error detection and 1-bit error correction.

(3) Prior Art and Problems Conventionally, an apparatus shown in FIG. 1 has been used to perform error detection or error detection and error correction as described above. That is, 8-bit data and 5-bit check bits added to the data are stored in memory 1, and this data is read out by ECC block circuit 2 to detect data errors and correct 1-bit errors. Note that when there is a 2-pit error, the ECC block circuit 2 generates an en-detection signal.

By the way, in the memory shown in Fig. 1, 2 (for example, 1 bit),
To obtain a 1 megabyte capacity using a memory element with an address capacity of 64, the memory element must be 8 x 16-1 for data.
28 (ke), 5 x 16 = 80 (ke) for check bit
A total of 9 pieces are required, resulting in a total of 208 pieces. However, checking all the bits in this way and allocating them to 3 bits is inefficient in the use of memory elements.
There is a problem that the memory cannot be made compact and the cost is high.

(4) Purpose of the Invention As stated above, the purpose of the present invention is to relatively reduce the number of memory elements in order to improve the problem that the utilization efficiency of memory elements in conventional memory devices is not very good. The present invention provides a memory device that improves the utilization efficiency of memory elements.

(5) Configuration of the present invention In order to achieve this object, the memory device of the present invention includes a storage means for storing data and a check bit corresponding to the data width in units of a data width that is an integral multiple of the access data width, and Error correction detection means sometimes generates a check bit corresponding to data of this data width and performs correction error detection for this data width during reading, and address desired access data from the data read from the storage means. selective reading means for selectively reading data specified by lower-order information; when writing access data to the storage means, the error correction detection means creates and writes check bits in units of the data width; The present invention is characterized in that when access data is read from the storage means, it is read in units of the data width to correct and detect errors.

(6) Embodiment of the present invention Before describing the present invention in detail based on an embodiment, the principle thereof will be briefly explained.

According to information theory, 1-bit error correction and 2-bit error detection are possible by adding 6 check bits to 16-bit data.

Therefore, instead of adding 5 bits of check bits to 8 bits of data, by adding 6 bits of check bits to 16 bits of data, the memory utilization rate can be improved from - to -13 22 be able to. The present invention is designed to improve the efficiency of memory usage by using the memory in such a state.

Next, one embodiment of the present invention will be described based on FIG.

FIG. 2 is a configuration diagram of this embodiment.

In the figure, 1' is a memory, and 2' is an ECC block circuit.

3 is a multiplexer.

Memory 1' stores 16-bit data transmitted from ECC block circuit 2', which will be described later, and 6 check bits added to the data at one address, and stores the data for addresses Ao-An-H. be. Here, these addresses are constructed by excluding the least significant bit of the address information compared to the addresses in the memory 1 of FIG.

The ECC block circuit 2' is the FCC block circuit 2 described above.
It has a data error detection and error correction function in the same way as the memory 1'. When reading data, the data and check bits are read out at the same time, and the check bits are used to correct 1-bit errors and detect 2-bit errors in the data. When writing or indulging these data, the write data to be accessed is 8
In the pit configuration, the 16 bits are divided into two according to the least significant bit AI of the address information, and one of them is specified.

The multiplexer 3 divides the 16-bit data read from the memory 1' by the ECC block circuit 2' into two using the least significant bits All of the address information, designates either one of the 8-bit data, and outputs the read data. It is.

Next, the operation of this embodiment shown in FIG. 2 will be explained.

■ When writing 8-bit data First, a write signal is transmitted from the outside to the ECC block circuit 2', and thereby all addresses A are written. The data stored at the address designated by address ~A, 1 of -An is read out and input to the ECC block circuit 2'. The ECC block circuit 2' selects 8 bits of write Φ data from among the 16 bits of data inputted to one 8 bits of the least significant bits of all addresses Ao""An, which is specified by "0". Rewrite. Then, in this ECC block circuit 2', 6 check bits are determined for 16 bits of data consisting of the rewritten data and the other 8 bits of data that have just been read. These data and check bits are then written to the designated address in the memory 1'. At this time, write data is written into one 8 bits of the memory 1', and the previous data is stored in the other 8 bits. To write other write data to the other 8 bits, read the written data and the other 8 bit data to the ECC block circuit 2' in the same way as above, and this time set the least significant bit An to 11. ” to specify the other 8 bits and rewrite this data to write data. Then, check bits are determined for the 16-bit wide data consisting of these two write data, and these data and check bits are assigned to address A (
, ”+Write to the address specified by Al1-1.

■ When reading 8-bit data, first, a read signal is transmitted from the outside to the ECC block circuit 2', and this causes the 16-bit data of the address specified by all addresses ~A~my address~AI, . is input to the ECC block circuit 2'. The ECC block circuit 2' performs a check bit error detection to see if there is an error between the input data and the data written to the memory 1'. When the data is corrected, the data is output to the multiplexer 3. At this time, one of the 8 bits is designated by rOJ of all the address holes 0 to 4, for example, the lowest bit (A), and the desired read data is output from the multiplexer 3. At this time, when the BCCCC clock circuit 2' detects a 2-bit error in the data, the ECCCC clock circuit 2' generates a Scherrer detection signal.

As mentioned above, if the check bit for 16-bit data is only 6 bits, we can use 7 to use 2 pieces of 8-bit data instead of 16-bit data, so conceptually it is shown in Figure 3. As shown, for 8-bit data, 3 check bits are sufficient.
The ratio of the number of check pits to the number of data pits can be reduced. Looking at this in terms of the number of memory elements, when configuring a memory with a capacity of 1 megabyte using memory elements with an address capacity of 64 bits, the memory elements will be 16 x 8 = 128 (ke) for data and 6 x for check pits.
8=48(k)1, totaling 176(k), making it possible to reduce the number of memory elements by 32 than the memory shown in FIG.

(7) As explained in detail about the invention, the present invention ultimately involves assembling access data as data with a number of bits that is an integral multiple of the number of bits that constitute this access data, and converting this data into data that has a number of bits that is an integral multiple of the number of bits that constitute this access data. Since error detection or error detection and error correction are performed using the number of check bits corresponding to the number of data bits, it is possible to perform error detection or error detection and error correction of each access data, so the ratio of the number of check bits to the number of data bits is can be reduced. Therefore, the number of memory elements for check bits can be reduced, contributing to cost reduction of the memory device. Furthermore, by reducing the number of memory elements in this way, the probability of errors caused by the memory elements of a memory device constructed from these memory elements also decreases. This also improves the reliability of the memory device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional memory device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 6 is a conceptual block diagram thereof. In the figure, 1 and 1' are memory, 2 and 2' are EC
In the C block circuit, 3 is a multiplexer. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani

Claims (1)

[Claims] fi+ Storage means for storing data and check bits corresponding to this data width in units of a data width that is an integral multiple of the access data width, and generating check pits corresponding to data of this data width during writing. and error correction detection means for performing error correction and error detection for this data width when reading. Selective reading means for specifying and selectively reading out desired access data from the data read from the storage means using lower-order information of the address information, and when writing the access data to the storage means, the error correction detection means Create and write a check bit in the above data width unit by
A memory device characterized in that when access data is read from the storage means, it is read and output in units of the data width to correct and detect errors.