JPH0756816A - Controller for memory - Google Patents

Abstract

PURPOSE:To enable normal access from an outside by setting the error flag of an address when one-bit error is detected, writing an address shown at an address pointer in a data part and writing correct data in this address. CONSTITUTION:When one-bit error is detected by an error detecting and correcting circuit 2, an error processing part 4 sets the error flag to an error flag part 13 of a memory 1. Next, an alternate address shown by an address pointer 3 is written in a part, where no error is generated, at a data part 11, the correct data are stored in the alternate address of an alternate area 14, and the value of the address pointer 3 is increased. On the other hand, the error processing circuit 4 outputs the correct data from the error detecting and correcting circuit 2 to the outside. When the error flag is set to the address at the time of access to the memory 1, an error address processing circuit 5 performs access to the alternate area while referring to the alternate address of that address, and the correct data of the alternate address are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, and more specifically, it performs reliability check by performing an error check on the data read from the memory and correcting the data when an error occurs. The present invention relates to a memory control device having improved performance.

[0002]

2. Description of the Related Art Conventionally, EDC (ERROR DETECTION) has been used as a technique for improving the reliability of a memory.
AND CORRECTION) was there. EDC is performed in the following procedure. When writing data to the memory, check data is generated by taking an exclusive OR between adjacent bits of the data. Then, the data and the check data are linked and written to the same address. The data and check data are read from this address. The exclusive OR operation is performed on the read data as in the case of generating the check data. The data obtained as a result of the calculation is compared with the read check data. Based on the result of collation, it is determined whether an error has occurred in the read data. By performing the exclusive OR operation on the data, when there is an error in the data, even the error location can be detected. One of EDC is SECDED (SIN
GLE ERROR CORRECT DOUBLE E
RROR DETECT). SECDED is 1
This is a method of correcting a bit error, and notifying the error when there are two or more bits. SECDED is widely used because its hardware configuration is not so large and it is suitable for practical use.
However, if an error occurs in a different bit in the same address where a 1-bit error occurs, normal access to that address becomes impossible. As a solution to this, there is EDC for 2-bit error detection and 3-bit error correction. However, this EDC requires a large hardware configuration.

[0003]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and normal access from the outside is possible even if an error occurs in different bits of data within the same address. It is an object of the present invention to realize a control device for various memories without increasing the hardware configuration.

[0004]

SUMMARY OF THE INVENTION According to the present invention, in a memory controller for performing error check on data read from a memory and correcting the data when an error occurs, a data section for storing the data itself is provided. , An ECC data part that stores data for detecting a 1-bit error of data and data for correcting a 1-bit error of the data, an error flag part that stores an error flag indicating the presence or absence of a 1-bit error in the past, and a 1-bit error When a 1-bit error is detected, the data is corrected on the basis of the memory composed of the alternative area for storing the data obtained by correcting the generated data and the contents read from the data part and the ECC data part of the memory. It shows the error detection and correction circuit and the address of the corrected data storage destination. This address is the address in the alternate area. Address pointer and the error detection / correction circuit detects a 1-bit error, an error flag is set in the error flag part of the memory, the address indicated by the address pointer is written in the data part, and this address is written to this address. If an error flag is set in the error flag portion when reading data from the memory, an error processing circuit that accesses and corrects data and writes the value of the address pointer is increased.
An error address processing circuit for accessing an address written in a data section and outputting the data stored at this address as correct data.

[0005]

According to the present invention, when a 1-bit error is detected at the read address when the memory is read, the error flag of this address is set and the address pointer is set in the data section. Write the address shown in, write the correct data to this address, and increment the value of the address pointer. If the error flag is set at the read address,
By referring to the address read from the data portion of this address, this address is accessed to read and output correct data.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
FIG. 1 is a configuration diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a memory, and a data section 11, an ECC data section 12, an error flag section 13, and a substitute area 14 are provided for each address. Data part 11
The data itself is stored in. ECC data section 12
Stores 1-bit error detection data of data and 1-bit error correction data of data. The 1-bit error detection data and the 1-bit error correction data are the data for performing the SECDED described above.
The error flag portion 13 stores an error flag indicating whether or not a 1-bit error has occurred in the past. Data obtained by correcting data in which a 1-bit error has occurred is stored in the alternative area 14. 2 is an error detection and correction circuit,
When a 1-bit error is detected based on the contents read from the data section 11 and the ECC data section 12 of the memory 1, the data is corrected. The error detection / correction circuit 2 notifies the error signal ERR that a 1-bit error is detected.
And the corrected correct data is output. Reference numeral 3 is an address pointer, which indicates an address (alternative address) of a storage destination of corrected data (correct data). The alternative address is an address in the alternative area 14. 4 is an error processing circuit,
When a 1-bit error is detected in the error detection / correction circuit 2 and an ERR signal is given, an error flag is set in the error flag part 13 of the memory 1, and the address pointer 3 indicates the part of the data part 11 where no error has occurred. The alternative address is written, correct data is stored in the alternative address in the alternative area 14, and the value of the address pointer 3 is increased. Further, the error processing circuit 4 outputs the correct data given from the error detection / correction circuit 2 to the outside. This data becomes the output data. Reference numeral 5 denotes an error address processing circuit which, when the memory 1 is accessed, if an error flag is set in the error flag part at the accessed address, substitutes by referring to the alternative address written in the data part of the address. Access the area and output the correct data stored at the alternate address. This data becomes the output data. After writing correct data to the alternate address, if a 1-bit error occurs in a bit different from the error bit in the written data, write a new alternate address in the data section at the alternate address, and Write the corrected data to another alternate address. In this way, every time a 1-bit error occurs, a new alternative address is assigned and the corrected data is written.

The operation of the thus constructed apparatus will be described. FIG. 2 is a flowchart showing the operation procedure. In FIG. 2, when reading out from the memory,
If the error flag is set in the read address, the alternative address read from the data section of this address is referenced, the alternative address is accessed, and correct data is read and output. If the error flag is not set in the read address but a 1-bit error is detected, the error flag is set in this address and the alternative address indicated by the address pointer is written in the data part. Then, the correct data is copied and written in the alternative address, and the value of the address pointer is increased. This correct data is output to the outside. When an error of 2 bits or more is detected at the read address, the error is notified and the process ends. If the error flag is not set at the read address and no error is detected, the data is output as it is. In this way, processing is performed according to the type of error.

[0008]

According to the present invention, when a 1-bit error is detected when a memory is accessed, the data of the address in which the error occurred is corrected and saved in another alternative address having no error to cause the error. The save destination address is written in a part of the address. When a 1-bit error occurs in a bit different from the bit in which the error has occurred in the data written in the save destination address, a new alternative address is assigned and the corrected data is saved again in another place. As a result, if the error is within 1 bit, even if the error occurs in different bits within the same address, the memory can be normally accessed as long as the alternative address can be read. Further, in the EDC for 2-bit error correction and 3-bit error detection, 4 to 8 bits of check data are required for each address, whereas in the present invention, several bytes of alternate memory and 1 bit of storage for each address are stored. Since only the area is required, the reliability of the memory can be improved with a small hardware configuration. As described above, according to the present invention, even if an error occurs in different bits of data in the same address, a memory control device that can be normally accessed from the outside can be realized without increasing the hardware configuration. be able to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation procedure of the apparatus of FIG.

[Description of Codes] 1 memory 11 data section 12 ECC data section 13 error flag section 14 alternative area 2 error detection and correction circuit 3 address pointer 4 error processing circuit 5 error address processing circuit

Claims (1)

[Claims] 1. A data controller for storing data itself and detection of a 1-bit error in the data, in a memory controller for performing error check on the data read from the memory and correcting the data when an error occurs. Data and an ECC data part that stores data for correcting a 1-bit error, an error flag part that stores an error flag indicating the presence or absence of a 1-bit error in the past, and data in which data in which a 1-bit error has occurred is corrected A memory composed of an alternative area for storing the data and an error detection / correction circuit for correcting the data when a 1-bit error is detected based on the contents read from the data part and the ECC data part of the memory, and Indicates the address of the data storage destination, which is the address in the alternate area. And the error detection and correction circuit detects a 1-bit error, an error flag is set in the error flag part of the memory, the address indicated by the address pointer is written in the data part, and this address is accessed to correct it. An error processing circuit that writes the data that has been written and increases the value of the address pointer, and if the error flag is set in the error flag section when reading the data from the memory, the address written in the data section is accessed, and An error address processing circuit for outputting data stored at an address as correct data, and a memory control device.