JPH07262794A - Memory device - Google Patents

Abstract

PURPOSE:To prevent the degradation in the use efficiency of memories and improve the reliability of data by building an error correcting circuit into a memory chip and writing the data after correcting the data. CONSTITUTION:An address latch 1 and an address decoder 3 select a memory cell 9 by the command of a control circuit 5 in the case of writing of the data. This control circuit 5 writes the data from an input/output data bus via an input/output sense amplifier 7 into the selected cell 9. In such a case, the data error detection correcting circuit 11 also forms an SEC-DEC code and writes this code into the cell 9. The cell 9 is selected by the command of the control circuit 5 in the case of reading out of the data. The control circuit 5 reads the data out of the cell 9 and reads out the SEC-DEC code as well. The control circuit 5 collates the bits of the data and the SEC-DEC code after reading out. The correcting circuit 11 corrects the error and the data is written into the cell 9 by the control circuit 5 when the error is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device provided in an information processing apparatus, and more particularly to a memory capable of reading and writing data at any time and a memory capable of reading and writing data at any time requiring refreshing of data. The present invention relates to a storage device in which an error correction circuit that detects and corrects an error in data stored in a memory chip is built in a memory chip.

[0002]

2. Description of the Related Art In recent years, the storage capacity of memories has increased remarkably. When increasing the storage capacity of the memory, there is a method of using a large number of memory chips or increasing the storage capacity per unit volume of the memory chips. The method of increasing the storage capacity per unit volume of the memory chip normally uses a random access memory (dynamic RAM) that needs refreshing. The dynamic RAM stores data depending on whether or not electricity is stored in the capacitor of the memory cell, so that electricity stored in the capacitor is discharged by normal natural radiation to destroy the data. In order to prevent data destruction due to the above-mentioned discharge, an error correction circuit for correcting an error when reading data is provided outside the memory chip in order to maintain the reliability of the data. When the error correction circuit is provided outside the memory chip, the read data is only corrected, and the corrected data is not rewritten in the memory cell that stores the data.

[0003]

However, conventionally, since the error correction circuit is provided outside the memory chip, the circuit configuration of the memory device having the error correction circuit becomes complicated and it takes a long time to design the circuit. There is a problem that it is difficult to promote an increase in cost and miniaturization of a circuit. In addition, when data is read, the data is only corrected and the corrected data is not rewritten.Therefore, when data remains as an error, single bit errors continue to overlap and develop into uncorrectable multi-bit errors. However, there is a problem that the reliability of the data is deteriorated.

As a countermeasure against the above problem, it is possible to incorporate an error correction circuit in the memory chip. However, since the conventional memory chip has a narrow bus width, incorporating the error correction circuit increases the bus width, resulting in an increase in the size of the memory chip. Be invited. Further, since the number of bits of the circuit that corrects the error is an odd number, there is a problem that the efficiency of use of the memory is reduced.

The present invention has been made in view of such conventional problems, and an object thereof is to prevent the circuit configuration of the storage device from becoming complicated by incorporating an error correction circuit in the memory chip. , Shorten the circuit design period and prevent cost increase. It is another object of the present invention to provide a storage device that prevents deterioration of memory usage efficiency and improves reliability of data stored in the memory.

[0006]

In order to achieve the above object, the first invention according to claim 1 is an error for detecting and correcting an error of data stored in a memory in which data can be read and written at any time. Error detection / correction data generation means for generating detection / correction code data, and error by comparing the error detection / correction code data generated by the error detection / correction data generation means with the data read from the memory An error correction circuit that includes an error detection unit that detects an error and an error correction unit that corrects the data in which the error is detected when the error detection unit detects an error. The gist is to write the data corrected by the above into the memory.

According to a second aspect of the present invention, there is provided a refresh counter for storing an address at the time of refresh of a memory capable of reading and writing data requiring data refresh at any time, and a refresh counter stored in the memory at the time of refresh. Error detection / correction data generating means for generating error detection / correction code data for detecting and correcting an error in the present data, error detection / correction code data generated by the error detection / correction data generation means, and Error detection means for detecting an error by collating with the data read from the memory by the address stored in the refresh counter at the time of refresh, and when the error detection means detects the error, corrects the detected error data. An error correction circuit having an error correction means for And, the gist to write the corrected data at the time of the refresh by the error correction circuit to the memory.

According to a third aspect of the present invention, a check bit generation for generating a check bit for an error detection / correction code for detecting and correcting an error in data stored in a memory capable of reading and writing data at any time Means for detecting an error by collating the check bit for error detection and correction code generated by the check bit generation means with the bit of the data read from the memory; and the error detection means for detecting an error. An error correction circuit having bit inversion means for inverting an error-detected data bit when it is detected is built in a memory chip, and the bit data corrected by the error correction circuit is written in the memory. Is the gist.

According to a fourth aspect of the present invention, there is provided a refresh counter for storing an address at the time of refresh of a memory capable of reading and writing data requiring data refresh at any time, and a refresh counter stored in the memory at the time of refresh. Check bit generation means for generating a check bit for an error detection correction code for detecting and correcting an error in the stored data, a check bit for an error detection correction code generated by the check bit generation means, and a refresh counter at the time of refreshing. Error detecting means for detecting an error by collating the bit of the data read from the memory with the address stored in the memory, and inverting the bit of the data in which the error is detected when the error is detected by the error detecting means. Error correction circuit having bit inverting means for The built in memory chips, and summarized in that write bits of data corrected by the error correction circuit to the memory during the refresh.

A fifth aspect of the present invention is summarized in that a check bit generator for generating a check bit for error detection and correction is used as the check bit generating means.

According to a sixth aspect of the present invention, the check bit for the error detection and correction code of the error detection means has an EC.
The gist is to use the C code.

A seventh aspect of the present invention is characterized in that a SEC-DED code, which is a kind of the ECC code, is used for the check bits for the error detection and correction code.

An eighth aspect of the present invention is summarized in that the bit inverting means uses a collector which inverts a bit of data in which an error is detected.

[0014]

According to the first aspect of the present invention, the data is stored in the memory which can be read and written at any time by the error detecting and correcting data generating means and the error detecting means of the error correction circuit incorporated in the memory chip. Data for error detection and correction code for detecting and correcting an error in existing data is generated. Then, the data for error detection and correction code generated by the error detection means is collated with the data read from the memory, and when an error is detected, the data is corrected and the corrected data is written in the memory. It is possible to prevent the circuit configuration of the storage device from becoming complicated and prevent the deterioration of the memory usage efficiency to improve the reliability of the data stored in the memory.

According to a second aspect of the present invention, an error detection / correction code is generated by an error detection / correction data generating means of an error correction circuit incorporated in a memory chip of a memory that can read and write data that requires data refreshing at any time. Data is generated. The generated error detection / correction code data is collated with the data read from the memory by the address stored in the refresh counter during the refresh. When an error is detected by the collation, the data in which the error is detected is corrected and the corrected data is written in the memory at the time of the refresh. Therefore, a memory (dynamic RAM) capable of reading and writing data that needs refreshing at any time is also available. Similar to the first aspect, it is possible to prevent the circuit configuration of the storage device from becoming complicated and prevent the deterioration of the memory usage efficiency to improve the reliability of the data stored in the memory.

Further, a third aspect of the present invention detects and corrects an error in the data stored in the memory in which the check bit generating means and the error detecting means of the error correction circuit built in the memory chip can read and write the data at any time. A check bit for the error detection / correction code is generated.
Then, the check bits for the error detection and correction code generated by the check bit generation means are collated with the bits of the data read from the memory, and when an error is detected, the bits of the data are inverted to correct the data. Since the data is written in the memory, it is possible to prevent the circuit configuration of the storage device from becoming complicated, and prevent the deterioration of the memory use efficiency to improve the reliability of the data stored in the memory.

The fourth aspect of the present invention is generated by the check bit generating means and the error detecting means of the error correction circuit incorporated in the memory chip of the memory that can read and write the data that requires data refreshing at any time. The check bit for the error detection / correction code is collated with the bit of the data read from the memory by the address stored in the refresh counter during the refresh. When an error is detected by the collation, the bit of the data in which the error is detected is inverted by the bit inverting means and the corrected data is written in the memory at the time of the refresh, so that the data requiring the refresh can be read and written at any time. Memory (Dynamic RA
Similarly to the first aspect of the invention, M) can prevent the circuit configuration of the storage device from becoming complicated, and can prevent the deterioration of the memory usage efficiency to improve the reliability of the data stored in the memory.

Next, according to the fifth aspect of the invention, since the check bit generator for generating the check bit for the error detection and correction code is used as the check bit generating means, it is possible to surely detect the data error bit by bit.

In the sixth and seventh inventions, an ECC code is used as a check bit for the error detection and correction code of the error detection means, and SEC-DED which is a kind of the ECC code.
Since the code is used, it is possible to reliably detect a data error.

In the eighth aspect of the invention, since the bit inverting means uses the collector which inverts the bit of the data in which the error is detected, the data error can be surely corrected.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing control according to an embodiment of a storage device of the present invention.

The storage device is provided in an information processing device and detects an error in data stored in a memory in which data can be read and written at any time and a data in which data needs to be refreshed at any time can be read and written. An error correction circuit for correction is built in the memory chip. The memory device includes an address latch 1, an address decoder 3, a control circuit 5, and an input / output sense amplifier 7.

The address latch 1 is an external CPU
An address (column address) designated by an address bus (not shown) is latched. The address decoder 3 selects one column address of the memory cell 5 from the column addresses latched by the address latch 1. The control circuit 5 controls the entire memory chip such as the address latch 1. The input / output sense amplifier 7 performs reading or writing on one column of the memory cell 9 described later according to the column address selected by the address decoder 3.

The memory device also includes a memory cell 9, a data error detection / correction circuit 11, and a check bit 13 for an error detection / correction code. The memory cell 9 is a capacitor (not shown) having a small structure for storing data in bit units.
The data is stored as "1" when electricity is stored in the capacitor and "0" when electricity is not stored in the capacitor. In the memory cell 9, capacitors are arranged in a matrix and the address decoder 3
The data is read or written by selecting the column address. A data error detection / correction circuit (hereinafter referred to as a detection / correction circuit) 11 collates data read at the time of reading or refreshing normal data with an error correction detection code described later to detect and correct an error in the data. The detection / correction circuit 11 writes the corrected data in the memory cell 9 under the control of the control circuit 5. The check bit for error correction detection code (hereinafter referred to as error check bit) 13 is a check bit for error correction detection code generated by a check bit generator 23 of the detection correction circuit 11, which will be described later. It is used when detecting and correcting errors.

The control of the detection / correction circuit 11 will be described with reference to the block diagram of FIG. The detection / correction circuit 11 includes a syndrome generator 15, an error bit locator 17,
A collector 19, a multiplexer 21, a check bit generator 23 and a collector 25 are provided. Further, the detection / correction circuit 11 has 5 check bits necessary for error detection under the control of the control circuit 5 for 16-bit data.

First, when data is written from the outside of the storage device, the check bit generator 23 is an error detection / correction code for each bit of the data to detect an error. The SEC-DED (Single Err
or Correction and Double Error Detection) code is generated. The generated SEC-DED code is the collector 25
Is written in the memory cell 9 via.

Here, the SEC-DED code is ECC (E
error correction code, which is a type of single error or double error detection code. It is an error correction method that can add a check bit to data to correct a 1-bit error and detect a 2-bit error. . In the figure, the number of check bits varies depending on the length of the data, but in the present embodiment, if 7 check bits are added to 32 bits of data from 0 to 31, 1 out of 39 bits
Bit errors can be corrected and 2-bit errors can be detected.

Next, when reading the data, the control circuit 5 reads and verifies the written error check bit 13 and the data. By the collation, the control circuit 5 refers to the error check bits 13 of the 7-bit check bits C0 to C6 indicated by "x" in the figure, and temporarily
If there is an error in one bit of the 32-bit data,
For example, 27 patterns are applicable when C0, C1 and C6 are different. Since the pattern 27 corresponds to the 27th bit of the 32 bits in the figure, the control circuit 5
Determines that the 27th bit is an error. When the 27th bit error is determined, the syndrome generator 15
A bit indicating an error is set at the 27th bit. Also, for example, when C0, C5, and C6 are different, the pattern corresponds to 17, and the control circuit 5 has 32 patterns.
Of the bits, the 17th bit is judged as an error. When an error is determined, the syndrome generator 15 sets a bit indicating an error in the 17th bit. Collector 1
Reference numeral 9 inverts the bits set by the syndrome generator 15 to correct the data and output the corrected data. The output data is written by the control circuit 5 via the multiplexer 21 and the collector 25.

Next, the operation of this embodiment will be described. First,
When writing data after turning on the power of the device, the address latch 1 and the address decoder 3 select the memory cell 9 according to the column address transmitted from the address bus in response to a command from the control circuit 5. The control circuit 5 writes the data transmitted from the outside via the input / output data bus via the input / output sense amplifier 7 into the memory cell 9 of the selected column address. In this case, the detection and correction circuit 1
The check bit generator 23 of 1 generates the SEC-DED code shown in FIG. 3 under the control of the control circuit 5 and writes it through the collector 25.

Next, when reading data, an address is latched in the address latch 1 by the control circuit 5 from the address bus and decoded by the address decoder 3 to select the column address of 1. The control circuit 5 reads out the data from the memory cell 9 from the selected column address of 1, and
Read the code. After reading the data, the control circuit 5 reads the bits of the read data and the SE shown in FIG.
Collate with C-DED code. For example, when the 27th bit error is detected in the data bits by the collation, the syndrome generator 15 of the detection correction circuit 11 is detected.
Sets the bit at the 27th bit. When a bit is set by the syndrome generator 15, the collector 19
Outputs the data after inverting the 27th bit to correct the data. The output corrected data is written in the memory cell 9 by the control circuit 5. When the error of the 17th bit is detected by the collation, the corrected data is written in the memory cell 9 via the syndrome generator 15 and the collector 19 as described above.

Next, another embodiment will be described with reference to the block diagram showing the control of FIG. The other embodiments described above have substantially the same configuration as the block diagrams shown in FIGS. 1 and 2 of the present embodiment, and a description of those having the same function will be omitted.

The other embodiment described above is characterized in that it is built in a random access memory (dynamic RAM) that requires refreshing (rewriting) to detect and correct an error at the time of refreshing, and simultaneously write the corrected data. And Another embodiment is shown in FIG.
Besides, a refresh counter 25 for storing an address to be refreshed is provided. The control circuit 5
The entire memory chip is controlled, a refresh command is output to a refresh counter 27 (described later) at the time of refreshing, an address for refreshing is output, and the address latch 1 is switched to the refresh counter 27 side. The switching causes the control circuit 5 to read the 1 column address output from the refresh counter 27 at a time, and then write control the refreshed address. The multiplexer 21 outputs the data read from the memory cell 5 at the time of refresh to the collector 25. The collector 25 inverts a bit indicating an error when an error bit of data is detected during refresh.

Next, the operation at the time of refreshing of another embodiment will be described. First, the control circuit 5 outputs a refresh command to the refresh counter 27, switches the address latch 1 to the refresh counter 27 side, and outputs the address to be refreshed to the address decoder 3. When the output address to be refreshed is decoded by the address decode 3, the control circuit 5
Reads data from the memory cell 9 from the refreshed one column address. After reading, the control circuit 5 collates the bit of the data read by the input / output sense amplifier 7 with the SEC-DED code. When the bit in which the error has occurred is detected in the data by the collation, the syndrome generator 15 of the detection / correction circuit 11 is detected.
Is 2 when the error bit is, for example, the 27th bit.
Set the bit at the 7th bit. When a bit is set by the syndrome generator 15, the error bit locator 17 causes the collector 25 to output a signal indicating a data error.
Output to. On the other hand, the read data is output to the collector 25 via the multiplexer 21 via the 16-bit data line. The collector 25 inverts the bit in which the error occurred and corrects the corrected data.
Is written in the memory cell 5.

As a result, since the error correction circuit is built in the memory chip, the circuit configuration of the memory device is prevented from becoming complicated and the memory is prevented from being complicated as compared with the conventional case where the error correction circuit is provided outside the memory chip. It is possible to prevent the deterioration of the use efficiency of and to improve the reliability of the data stored in the memory.

In addition, a memory (dynamic RA
Similarly, in M), the circuit configuration of the storage device can be prevented from becoming complicated, and the efficiency of use of the memory can be prevented from being lowered to improve the reliability of the data stored in the memory.

Furthermore, if an error is detected and corrected at the time of refreshing, it can be handled in the same manner as a memory chip that does not have an error correction circuit incorporated therein without being aware of it from the outside.

Since the syndrome generator 15 of this embodiment and other embodiments sets a bit at the bit position of the data in which the data stored in the memory cell 9 is destroyed by the natural radiation, the error bit of the data is surely detected. Can be recognized by.

The error bit locator 17 also collects signals indicating an error when the syndrome generator 15 sets a bit indicating an error.
Since it is output to, the error of the data can be surely transmitted. Collector 19 when writing data to memory
Since the error bit is inverted by 25, the data in which the error is detected can be surely corrected.

Further, the check data generator 23
Generates a SEC-DED code which is a check bit for an error detection / correction code for checking an error, so that the error can be detected in bit units. The multiplexer 21 outputs the data read from the memory cell 9 at the time of refresh to the collector 25 and the check bit generator 23, so that the error can be detected and corrected at the same time as the refresh.

Refresh counter 27 of another embodiment
Supplies the address when refreshing, so that the refresh operation can be ensured.

Since the memory device having the error correction circuit of this embodiment and the other embodiments incorporated therein can be handled in the same manner as a normal memory chip, it can be mounted on various electric products and mechanical products.

[0042]

As described above, according to the first aspect of the invention, an error correction circuit is built in a memory chip, and data for error detection and correction code is collated with data read from the memory to detect an error. Then, the data is corrected and the corrected data is written in the memory, so that the circuit configuration of the storage device is prevented from becoming complicated, and the circuit design period is shortened to prevent cost increase. In addition, it is possible to prevent a decrease in memory usage efficiency and improve reliability of data stored in the memory.

A second aspect of the invention is to incorporate an error correction circuit in a memory chip of a memory capable of reading and writing data that requires data refresh at any time, and to provide data for error detection and correction code and the memory at the time of refresh. When an error is detected by collating with the data read from the device and the error-detected data is corrected and the corrected data is written in the memory, the data requiring refreshing can be read and written at any time. Similarly to the first aspect of the invention, the memory (dynamic RAM) prevents the circuit configuration of the storage device from becoming complicated, and
Shorten the circuit design period and prevent cost increase. In addition, it is possible to prevent a decrease in memory usage efficiency and improve reliability of data stored in the memory.

Further, in the third invention, when an error correction circuit is built in the memory chip and the check bit for the error detection / correction code is collated with the bit of the data read from the memory, an error is detected. Since the bit of the data is inverted and the corrected bit data is written in the memory, the circuit configuration of the storage device is prevented from becoming complicated, and
Shorten the circuit design period and prevent cost increase. Further, it is possible to prevent a decrease in memory usage efficiency and improve reliability of data stored in the memory.

In a fourth aspect of the present invention, an error correction circuit is built in a memory chip of a memory that can read and write data at any time that requires data refresh, and a check bit for an error detection and correction code and at the time of the refresh. When an error is detected by collating the bit of the data read from the memory, the bit of the data in which the error is detected is inverted, and the data of the corrected bit is written in the memory at the time of the refresh, so refresh is necessary. Similarly to the first invention, the memory (dynamic RAM) capable of reading and writing data at any time prevents the circuit configuration of the storage device from becoming complicated and shortens the circuit design period to prevent cost increase. Further, it is possible to prevent a decrease in memory usage efficiency and improve reliability of data stored in the memory.

Next, in the fifth aspect of the invention, since the check bit generator for generating the check bit for the error detection and correction code is used in the check bit generation means, it is possible to surely detect the data error in bit units.

In the sixth and seventh inventions, an ECC code is used as a check bit for the error detection and correction code of the error detection means, and SEC-DED which is a kind of the ECC code.
Since the code is used, it is possible to reliably detect a data error.

In the eighth aspect of the invention, since the bit inverting means uses the collector which inverts the bit of the data in which an error is detected, the data error can be surely corrected.

[Brief description of drawings]

FIG. 1 is a block diagram showing control according to an embodiment of a storage device of the present invention.

FIG. 2 is a block diagram showing control of a data error detection / correction circuit 11.

FIG. 3 is a diagram showing an error correction code.

FIG. 4 is a block diagram showing control of another embodiment.

[Explanation of symbols]

 1 Address Latch 3 Address Decoder 5 Control Circuit 9 Memory Cell 11 Data Error Detection and Correction Circuit 13 Check Bit 15 Syndrome Generator 17 Error Bit Locator 25 Check Bit Generator 27 Refresh Counter

Claims (8)

[Claims] 1. An error detection / correction data generation unit for generating data for an error detection / correction code for detecting and correcting an error in data stored in a memory in which data can be read / written at any time, and the error detection / correction data generation unit. Error detection means for detecting an error by collating the data for error detection and correction code generated by the data generation means with the data read from the memory; and when an error is detected by this error detection means, an error is detected. Error correction means for correcting the stored data, and an error correction circuit including the
A storage device, wherein the data corrected by the error correction circuit is written in the memory. 2. A refresh counter for storing an address at the time of refresh of a memory capable of reading and writing data at any time requiring data refresh, and detecting and correcting an error of the data stored in the memory at the time of refresh. Error detection / correction data generation means for generating data for error detection / correction code, error detection / correction code data generated by the error detection / correction data generation means, and address stored in the refresh counter at the time of refreshing Error detecting means for detecting an error by collating the data read from the memory with the error detecting means, and error correcting means for correcting the data in which the error is detected when the error detecting means detects an error. By incorporating the correction circuit in the memory chip,
A storage device, wherein the data corrected by the error correction circuit is written in the memory at the time of refreshing. 3. A check bit generation unit for generating a check bit for an error detection correction code for detecting and correcting an error in data stored in a memory in which data can be read and written at any time, and generated by this check bit generation unit. Error detecting means for detecting an error by collating the check bit for the error detecting and correcting code and the bit of the data read from the memory, and the error detected data when the error detecting means detects the error. A bit inverting means for inverting the bits of, and an error correction circuit comprising:
A storage device, wherein bit data corrected by the error correction circuit is written in the memory. 4. A refresh counter for storing an address at the time of refresh of a memory capable of reading and writing data requiring data refresh at any time, and detecting and correcting an error of the data stored in the memory at the time of refresh. Check bit generating means for generating check bits for the error detection and correction code, and check bits for the error detection and correction code generated by the check bit generation means and the address stored in the refresh counter at the time of refreshing from the memory. An error detecting means for detecting an error by collating with a bit of data to be read, and a bit inverting means for inverting the bit of the data in which the error is detected when the error detecting means detects an error. Built-in correction circuit in the memory chip ,
A storage device characterized in that bit data corrected by the error correction circuit is written in a memory at the time of refreshing. 5. The storage device according to claim 3, wherein the check bit generating means uses a check bit generator for generating a check bit for an error detection / correction code. 6. The storage device according to claim 3, wherein an ECC code is used as a check bit for an error detection / correction code of said error detection means. 7. The storage device according to claim 6, wherein a SEC-DED code which is a kind of the ECC code is used for the check bit for the error detection and correction code. 8. The storage device according to claim 3, wherein the bit inverting means includes a collector which inverts a bit of data in which an error is detected.