JP3170145B2 - Memory control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention divides a storage area in a memory element into two storage units having the same capacity in a computer system so that the same correct data is stored in each storage unit. The present invention relates to a control method of a memory device.

[0002]

2. Description of the Related Art In the field of semiconductor devices, microfabrication techniques have been remarkably advanced. In various memory elements, the storage capacity per memory element increases due to the progress of the miniaturization technology, but the amount of accumulated charge decreases due to the reduction in the volume occupied by one memory cell, and the probability of occurrence of minute defects increases. Due to external factors such as the application of electrical noise accompanying the high-speed operation, the probability of occurrence of error bits in data increases.

[0003] Generally, as a method of improving data reliability in a memory device, a parity check method and an ECC are used.
Mechanisms are known. In the parity check method, one parity bit is added to a data bit, and the number of bits in which the value of the data bit and the parity bit is “1” is unified to an odd or even number by the parity bit, and the parity bit is applied to the memory device. At the time of writing and reading, an error is detected by checking the number of bits in which the value of the data bit and the parity bit is "1".

In the ECC mechanism, a check bit is generated from a data bit using an extended Hamming code, the data bit and the check bit are written into a memory device, and a syndrome is generated from the data bit and the check bit read from the memory device at the time of reading. 1-bit error correction and 2-bit error detection are performed from this syndrome.

[0005]

However, according to the parity check method, only odd-numbered bit errors can be detected, and even-numbered bit errors cannot be detected. There was a drawback that the error could not be corrected because it was not possible to specify whether there was an error. Also,
The ECC mechanism can perform 1-bit error correction and 2-bit error detection, but cannot detect 3-bit or more errors, and increases the number of gates of a syndrome generation circuit for determining the presence or absence of a data error. There were drawbacks.

The present invention solves these disadvantages of the prior art and provides a memory capable of detecting and correcting errors in all bits of data read from a memory element by an error detection circuit using a small number of logic gates. An object of the present invention is to provide a control method of a device.

[0007]

According to the present invention, there is provided a memory device in which a storage area is divided into two storage units having the same address space by utilizing an increase in storage capacity, and a memory device which stores data read from each storage unit. An error detection unit for detecting an error in the read data and transmitting valid data by taking an exclusive OR for each bit; an error bit designation register for storing the position of the error bit in the read data; A data storage register for storing data read from the unit, an address register for storing an address at the time of memory access, and a memory control circuit using a microcomputer for correcting an error bit in the read data. I do.

That is, a memory control system according to the present invention
Beam is a storage area with the first having the same address space and memory device divided into a second storage unit, the address of the same address space of the first and second storage units simultaneously or individually be designated and addressing means, the address register for storing an address of the same address space when the memory access, first and second data storage for storing data read from said first and second storage units wherein means and, error detection means for performing error detection of the read data, an error bit storage means for storing the position of the error bit in the read data, an error correction means for performing correction of the error bits in the read data, the <br/> error detecting means, an exclusive oR for each bit of data read from the same address of said first and second storage units And outputs a error detection signal when at least exclusive OR of one bit is "1",
The addressing means outputs the error detection signal.
The address stored in the address register.
The address of the first storage unit individually
Is intended to, said error correction means, when the error detection signal is output, the addressing means is specified separately
The address of the first memory unit in which, after writing the inverted data of each bit of the data stored in the first data storage means, reads the inverted data written, the the read inverted data by comparing the pre-reversal data in the first data storage means, bit values match between the inverted data and said anti <br/> rolling before data is hard error
The address designating means,
When the error detection signal is output, the address register
The second storage unit based on the address stored in the second storage unit.
The address of the packet is specified individually, and the error
When the error detection signal is output, the correction means outputs the error signal.
The second storage unit individually designated by the dress designation means.
Bets address, said after writing the inverted data of each bit of the data stored in the second data storage means, reads the inverted data written, read inverted data and said second data storage means by comparing the pre-inversion data of the inner, bit values match between the inverted data and the inverted data before is intended to determine a hard error, the
The error correction means stores all the bits stored as errors in the error bit storage means as the first and second bits , respectively.
And any one of the storage units of the second storage unit
In the case in which it is determined that the hard error, a value after correction of bits with the error bit, corresponding said first or second data storage means data
Of the bits, by selecting the value of bi <br/> Tsu bets that are not deemed to be a hard error, performs data correction
It is characterized by being.

Also, a memory control according to the present inventionsystem
IsTwo storage areasMemory element divided into storage units
With the child,SaidTwo storage units,Same address spaceTo
Assigned in common and to the two storage units,Previous
Converted from the same address spaceSaidTwo memory units
A unique address spaceRespectivelyAddress to assign
Coder and the same address space at the time of memory access
Address register for storing the address of the
Error detection including registers, error detection circuits and signal selection circuits
Output unit, error bit designation register, and microcomputer
Embedded memory control means,The two storage units
When writing data,The same ad
Address in the address spaceaddressSame dataTo
The error detection circuit,Data reading
When out,For addresses in the same address spaceSaid
From two storage unitsRespectivelyOf the read data
Read data error by exclusive OR for each bit
DetectionThe signal selection circuit,No error
WhenAnd saidData read from two storage units
Sends one of the data as valid dataTo do
And the error detection circuit includes:When there is an error,Error detection signal
Activate the issueWherein the memory control means
When the error detection signal is activated,Data storage cash register
StarSaidFrom two storage unitsRespectivelyRead out
Memorized data,SaidError bit specification registerSaid
Stores the position of the error bit in the read data.,The same
Exists outside one address spaceThe twoStorage unitTo
RespectivelySpecify assigned specific addressTo do
And the address decoder, the specific address and the
Address stored in address registerBased on the previous
Specify the corresponding addresses of the two storage units.
Wherein the memory control means
The address decoder for each storage unit
To the address specified byData in data storage register
Write and read inverted data of "0" and "1" for each data bit
Read out and read inverted dataSaidData storage
Performs comparison with the data before inversion in the register.
FruitSaidWith inverted dataSaidValues match between data before inversion
Bit is a hard errorAnd that
And the memory control means,Error bit storage means
All bits stored as errorsBut
Of any one of the two storage units
Is determined to be a hard errorIf
Contains the value of each bit in the data.After correctionAs a valueAnd saidDe
Data storage registerOf the corresponding bits of the two data
home,Hard errorWas not determinedSelect bit value
By choosing,Corrects data and sends corrected data
Activate the error correction enable signal and error correction end signal
Is the thingIt is characterized by the following.

The error bit storage means or the error bit designation register is not always necessary. If the error bit storage means is omitted, the first and second error correction means may be used.
Then, the data stored in the data storage means may be compared, and a bit whose value does not match may be determined as an error bit. When the error bit designation register is omitted, the two data stored in the data storage register may be compared by the memory control means, and a bit whose value does not match may be determined as an error bit. Using the information of the error bit, it is possible to distinguish between a hard error and a soft error.

[0011]

According to the present invention, two storage units having the same address space store the same data, and the exclusive OR for each bit of the read data from each storage unit is obtained to obtain the read data. Check for identity. By taking the logical sum of the outputs of the exclusive OR, the error detection signal is activated when there is at least one bit whose output of the exclusive OR is "1". It can be carried out.

Further, since the error detection of the read data is performed by taking the logical sum of the output of the exclusive OR for each bit of the read data, the error detection circuit can be configured with a smaller number of gates than the ECC mechanism. . Also, when an error is detected in the read data, the memory control circuit using a microcomputer corrects the error in the read data.
Data error correction can be performed without saving the data in the CPU. In addition, the use of a microcomputer enables flexible control, and the amount of hardware for correcting errors in read data in the memory control circuit can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, wherein 1 is a memory element, 1a and 1b are divided storage areas of the memory element 1, have the same address space, have the same storage capacity, and store the same data. Unit A and storage unit B. Each of the storage units 1a and 1b has a unique address space indicating a physical position in the memory element, separately from the same address space. An address decoder 2 converts addresses in the same address space of the storage units 1a and 1b at the time of memory access to corresponding addresses in a unique address space of the storage units 1a and 1b. Reference numeral 3 denotes an address register, which is a storage unit 1 at the time of memory access.
The addresses in the same address space of a and 1b are stored.

Reference numeral 4 denotes an error detection unit, and the storage unit 1
An error is detected by taking an exclusive OR for each bit of the data read from a and 1b. When there is an error, the error detection signal 11 is activated. When there is no error, one of the data read from the storage units 1a and 1b is selected and sent to ten data lines as valid data. 5
Determines whether the error correction of the read data is possible when the error detection signal of 11 is activated by the memory control circuit using the microcomputer, and if the read data can be corrected, corrects the read data and corrects the corrected data. Send out. 6a,
Reference numeral 6b denotes a data storage register A and a data storage register B for storing read data from the storage units 1a and 1b, respectively. 7 is an address register read line, 8a,
8b is a data line of the storage unit A, a data line of the storage unit B, and 9a and 9b are a read line of the data storage register A and a read line of the data storage register B. Reference numeral 12 denotes an error correctable signal, which is activated by the memory control circuit 5 when an error in the read data can be corrected. An error correction end signal 13 is activated by the memory control circuit 5 when the error correction procedure ends. 14 is an address line. 1
Reference numeral 5 denotes an error bit designation register that stores the position of an error bit when there is an error in the read data. Reference numeral 16 denotes an error bit designation register read line.

FIG. 2 shows an example of allocation of the same address space of the storage units 1a and 1b and a unique address space of the storage units 1a and 1b. In this example, the same address space is 10000 to 10FFF, the unique address space of the storage unit 1a is 0000 to 00FFF, and the unique address space of the storage unit 1b is 01000 to 01F.
FFs have the same space capacity. Storage units 1a, 1b
The unique address space represents a physical position in the memory element, and continuous physical addresses of the memory element 1 are divided by the unique address spaces of the storage units 1a and 1b, respectively. The unique address spaces of the storage units 1a and 1b both correspond one-to-one with the same address space in ascending order of address.

That is, in the example of FIG.
a the minimum address 0000 in the unique address space of the storage unit 1b and the minimum address 0 in the unique address space of the storage unit 1b
1000 is the minimum address 1000 in the same address space
0, each time the address in the unique address space of the storage unit 1a, 1b increases by one, the corresponding address in the same address space increases by one, and the maximum address 00FFF in the unique address space of the storage unit 1a. The maximum address 01FFF in the unique address space of the storage unit 1b is the maximum address 10F in the same address space.
Corresponds to FF.

Normal data writing is performed in the storage unit 1
This is performed by writing the same data to a and 1b. Normal data writing will be described with reference to FIG.
An address 1000 within the same address space is assigned to the address line 14.
1 by the address decoder 2 and the storage unit 1a
Of the storage unit 1b is converted into an address 00001 in the unique address space of the storage unit 1b. The write data on the data line 10 is represented by the address 00001 in the unique address space of the storage unit 1a and the address 01001 in the unique address space of the storage unit 1b through the storage unit A data line 8a and the storage unit B data line 8b. Write to storage area.

In normal data reading, the presence or absence of an error in the read data is checked by taking an exclusive OR for each bit of the data read from the storage units 1a and 1b by the error detection unit 4. If there is no data, one of the data read from the storage unit 1a and the storage unit 1b is sent to the data line 10 as valid data, and when there is an error, the error detection signal 11 is activated.

If there is an error, the address register 3
, An address in the same address space at the time of memory access is stored, and data read from the storage units 1a and 1b are stored in the data storage registers A and B of 6a and 6b, respectively. The position of the error bit in the read data is stored in the designation register 15, and the memory control circuit 5 using a microcomputer is used.
Judge whether or not the read data can be corrected, and if the read data can be corrected, correct the read data and send the corrected data.

The determination of the possibility of error correction of the read data and the correction of the read data are performed by writing and reading the inverted data of the read data when an error is detected in the storage unit 1a and the storage unit 1b alone. The data is compared with the read data at the time of error detection, which is the data before inversion, and the comparison is performed based on the result. FIG. 3 is a circuit diagram of the error detection unit 4 and an example of connection between the error detection unit 4 and the error bit designation register 15. In this example, it is assumed that 4-bit data is stored in a storage area represented by one address of storage units 1a and 1b, and storage unit A data line 8a, storage unit B data line 8b, All data lines 10 are 4 bits wide.

The error detection unit 4 includes a signal selection circuit 41
And an error detection circuit 42. Signal selection circuit 41
Is the distribution of write data on the data line 10 during normal data writing to the storage unit A data line 8a and the storage unit B data line 8b, and the storage unit A data when there is no error in the read data during normal data reading. Line 8a, storage unit B storage unit 1 on data line 8b
a, sending one of the read data from the storage unit 1b to the data line 10 as valid data, and sending the corrected data when the memory control circuit 5 corrects the error data to the data line 10.

The error detection circuit 42 performs an exclusive OR operation for each bit of data read from the storage units 1a and 1b on the storage unit A data line 8a and the storage unit B data line 8b during normal data reading. To check the identity of the read data. Error detection circuit 4
2 utilizes the fact that the probability that an error occurs simultaneously in the same bit in two different storage areas where the same data on the memory element is stored is extremely low, and the storage units 1a and 1b are used.
If the read data from the same is the same, it is determined that the read data is correct. When there is a difference between the data on the storage unit A data line 8a and the data on the storage unit B data line 8b, it is regarded as an error, and the output of the exclusive OR of the erroneous bits in the data becomes "1". The OR of the output of the exclusive OR of each bit is the error detection signal 11, and if there is even one bit error in the data, the error detection signal 11 is activated to "H". Since exclusive OR of all bits is obtained, error detection of all bits is possible.

Further, since the error detection method is simple,
An error detection circuit can be configured with a small number of logic gates. The error detection circuit of the present invention includes 32 2-input EX-OR gates and 31 2-input OR gates, assuming that 32-bit data is stored in a storage area represented by one address. You. Assuming that the ECC mechanism generates a check bit from a 16-bit exclusive OR of 32-bit data, 11 bits are required for error detection.
Two EX-OR gates and six OR gates are required. As a result, when the data is 32 bits, according to the present invention, 55 2-input gates can be omitted as compared with the ECC mechanism.

As shown in FIG. 3, the error detection circuit 42
Is output to the corresponding bit of the error bit designation register 15, and if there is an error bit in the read data, the corresponding bit of the error bit designation register 15 is set to "1". Is stored. In the example of FIG. 3, the data on the storage unit A data line 8a and the data on the storage unit B data line 8b are 1101, 10 respectively.
At 11, the first and second bits become erroneous, the error detection signal 11 is activated to “H”, and “1” is stored in the first and second bits of the error bit designation register 15.

A normal data read operation will be described with reference to FIGS. An address 10001 in the same address space is given to the address line 14, and an address 000 in the unique address space of the storage unit 1a is given by the address decoder 2.
01, is converted to an address 01001 in the unique address space of the storage unit 1b. Storage unit A data line 8
a, storage unit 1a on storage unit B data line 8b
The data stored in the storage area represented by the address 00001 in the unique address space of the storage unit 1b and the address 01001 in the unique address space of the storage unit 1b is read.

Next, the error detection unit 4 calculates the exclusive OR for each bit of the read data of the storage units 1a and 1b on the storage unit A data line 8a and the storage unit B data line 8b, thereby obtaining the read data. Is checked for errors. 3 and 5, the storage unit A data line 8a and the storage unit B data line 8b
In the upper data, the first bit and the second bit become errors at 1101 and 1011 respectively, and the error detection signal 11 is activated to "H". If the data on the storage unit A data line 8a and the storage unit B data line 8b are the same, it is determined that there is no error in the read data, and one of the data on the storage unit A data line 8a and the storage unit B data line 8b is replaced. The data is transmitted to the data line 10 as valid data. In the example of FIG. 5, since there is an error in the read data, the addresses in the same address space at the time of memory access on the address line 14 are stored in the address register 3, and the data storage registers A and 6b of 6a and 6b are stored. B, a storage unit A data line 8a and a storage unit B data line 8 respectively.
The read data on b is stored, and the position of the error bit in the read data is stored in the error bit designation register 15.

When an error in the read data is detected by the error detection unit 4 and the error detection signal 11 is activated to "H", the memory control circuit 5 using a microcomputer detects the error in the storage units 1a and 1b alone. Writing inverted data of "0" and "1" for each bit of read data at the time of
Read, compare the read inverted data with the read data at the time of error detection that is the data before inversion,
The data is corrected based on the result. The read data at the time of error detection is stored in the storage unit 1a,
The read data from 1b is stored in the data storage registers A and B of 6a and 6b.

A single access to the storage units 1a and 1b is performed by designating a specific address assigned to each storage unit. This specific address exists outside the same address space of the storage units 1a and 1b in order to distinguish it from a normal memory access. 6 to 9, the specific addresses of the storage units 1a and 1b are 40000 and 40001, respectively.

If there is a bit whose value matches between the inverted data and the read data at the time of error detection, which is the data before inversion, the bit is determined to be a hard error. If a bit stored as an error bit in the error bit designation register 15 does not match the value between the inverted data and the data read from the storage unit before writing the inverted data, the bit is determined to be a soft error. If there is no soft error and the bit where the hard error exists between the storage units 1a and 1b is different, it is determined that the error data can be corrected, and the error data is corrected.

[0030] Correction of erroneous data, the storage unit 1a at the time of error detection, the value of the bit hard error is present in reading data from the storage unit 1b, the corresponding bit value of the storage unit hard error is not present It is done by doing. When the correction of the error data is completed, the memory control circuit 5 sends out the correction data, and outputs the error-correctable signal 1
2 and the error correction end signal 13 are activated to "H". In the case where the soft error exists and the case where the bit in which the hard error exists between the storage units 1a and 1b matches,
When it is determined that the error data cannot be corrected, the memory control circuit 5
Only the error correction end signal 13 is activated to "H".

In the present invention, the memory control circuit 5 using a microcomputer determines whether or not error correction of read data is possible and corrects error of read data. Therefore, C
There is no need for the PU to determine whether or not the read data can be corrected for errors and for performing the read data error correction.
Since it is not necessary to save the data in the U, determine whether or not to correct the read data error, and read or execute the program for correcting the read data error, the processing capability of the computer system can be improved. Further, by using a microcomputer for the memory control circuit 5, flexible control becomes possible, and it is possible to reduce the enormous amount of hardware for determining whether or not to correct the read data error and for performing the error correction of the read data. it can.

The correction of erroneous data by the memory control circuit 5 using a microcomputer when an error is detected during normal reading will be described with reference to FIGS. The addresses and data used in the examples of FIGS.
The values are the same as those used in the example of FIG. FIG.
This is an example of writing inverted data of read data to the storage unit 1a when an error is detected. The data read from the storage unit 1a at the time of error detection is the data storage register A of 6a.
And 1101 in the example of FIG. The memory control circuit 5 accesses the storage unit 1a independently and writes the inverted data of "0" and "1" for each bit of the data. The position where the inverted data is written is the storage area from which the data was read by the storage unit 1a when the error was detected.

The single access to the storage unit 1a is performed by the memory control circuit 5 by the specific address 40 of the storage unit 1a.
000 is specified. Upon receiving the specific address 40000, the address decoder 2 stores the error detection storage units 1a and 1a stored in the address register 3.
1b in the same address space 10001
Address 000 in unique address space of storage unit 1a
Convert to 01. The memory control circuit 5 sends the inverted data 0010 of the data of the data storage register A of 6a to the storage unit A data line 8a, and writes the inverted data 0010 in the storage area of the storage unit 1a represented by the address 00001 in the unique address space.

FIG. 7 shows an example of writing inverted data of read data into the storage unit 1b when an error is detected. The writing of the inverted data is performed in the same manner as in the case of the storage unit 1a. In the example of FIG. 7, the data read from the storage unit 1b at the time of error detection is 1011 and the inverted data is 01.
00. FIG. 8 shows an example of reading the inverted data written in the storage unit 1a and comparing the read inverted data with the data before inversion. The reading of the inverted data written to the storage unit 1a is performed by the memory control circuit 5 designating the specific address 40000 of the storage unit 1a, as in the case of writing the inverted data to the storage unit 1a in FIG. In the example of FIG.
The inverted data written in a is read out to the storage unit A data line 8a as 0000. The data before inversion stored in the data storage register A 6a is 1101, and since the first bit matches between the inverted data and the data before inversion, the first bit is determined to be a hard error.

FIG. 9 shows an example of reading the inverted data written in the storage unit 1b and comparing the read inverted data with the data before inversion. In the same manner as in the case of the storage unit 1a, the reading of the written inverted data and the comparison between the read inverted data and the data before inversion are performed. In the example of FIG. 9, the inverted data written in the storage unit 1b is read as 0000, and the data before inversion is 1011. The second between inverted data and data before inversion
Since the bits match, the second bit is determined to be a hard error.

In FIG. 8 and FIG.
In No. 5, the values of the first and second bits are "1" and the first and second bits are designated as error bits. However, since the first and second bits are determined to be hard errors, the There are no errors. Also, the storage unit 1
Since the position of the bit where the hard error exists differs between a and the storage unit 1b, it is determined that the error data can be corrected.

FIG. 10 shows an example of error data correction by the memory control circuit 5. The data read from the storage units 1a and 1b at the time of error detection stored in the data storage registers A and B of 6a and 6b are 1101 and 1011 respectively. According to FIG. 8 and FIG.
In the storage units 1a and 1b, since a hard error exists in the first bit and the second bit, respectively, the values of the first bit and the second bit of the correction data are the values of the first bit of the data storage register B of 6b, respectively. "1", the value of the second bit of the data storage register A of 6a is "1". The 0th data read from the storage units 1a and 1b
Since the value of the bit and the value of the third bit match at "1",
The values of the 0th and 3rd bits of the correction data are “1”.

As a result, in the example of FIG. 10, the correction data is 1111. When the correction of the error data ends, the memory control circuit 5 sends the correction data 1111 to the storage unit A data line 8a, and activates the error correction enable signal 12 and the error correction end signal 13 to "H". The error detection unit 4 stores the corrected data 11 on the storage unit A data line 8a.
11 is transmitted to the data line 10, and the correction of the error data is completed.

In the above embodiment, the error bit designation register 15 and the error bit designation register read line 16 can be omitted. In that case, the memory control circuit 5 using a microcomputer performs the function, but the other points are the same as those of the above-mentioned embodiment. That is, the data read from the storage units 1a and 1b are read by the error detection unit 4. Is detected, the error detection signal 1
1 is activated to "H", and those read data are stored in the data storage registers 6a and 6b. The memory control circuit 5 compares the data stored in the data storage registers 6a and 6b for each bit, and detects a bit having a different value as an error bit.

Next, the memory control circuit 5 separates a hard error from a soft error in the same procedure as described above using the information of the error bit detected in this way. , 1b, when the bit in which the hard error exists differs, it is determined that the error data can be corrected, and the error data is corrected. When the correction of the error data is completed, the memory control circuit 5 sends out the corrected data, and activates the error correctable signal 12 and the error correction end signal 13 to "H". When a soft error exists and a bit in which a hard error exists between the storage units 1a and 1b matches, it is determined that error data cannot be corrected, and an error correction end signal is determined by the memory control circuit 5. Only 13 is activated to "H".

[0041]

As described above, according to the present invention, the same data is written to two storage areas of one storage element, and at the time of reading, the exclusive OR for each bit of the two data is obtained. Since error detection of read data is performed, error detection of all bits of the read data can be performed. Further, since the error detection method is simple, the error detection circuit can be configured with a smaller number of gates than the ECC mechanism. Furthermore, since the error correction of the read data is performed by the memory control circuit using the microcomputer, the error correction of the data can be performed without saving the data in the CPU, and the processing capability of the computer system can be improved. . Moreover, the use of a microcomputer enables flexible control,
The amount of hardware for error correction in the memory control circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a memory device according to the present invention.

FIG. 2 is a diagram showing an example of address assignment of storage elements.

FIG. 3 is a diagram showing a circuit configuration example of an error detection unit and a connection example of the error detection unit and an error bit designation register.

FIG. 4 is an explanatory diagram of data writing in a memory device.

FIG. 5 is an explanatory diagram of data reading of a memory device.

FIG. 6 is a view for explaining inversion data writing when a read data error is detected.

FIG. 7 is a diagram illustrating writing of inverted data when a read data error is detected.

FIG. 8 is a view for explaining inversion data reading when a read data error is detected and comparison between the inversion data and data before inversion.

FIG. 9 is a diagram for explaining inversion data reading when a read data error is detected and comparison between the inversion data and data before inversion.

FIG. 10 is a view for explaining correction of error data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory element 1a ... Storage unit A 1b ... Storage unit B 2 ... Address decoder 3 ... Address register 4 ... Error detection unit 5 ... Memory control circuit 6a ... Data storage register A 6b ... Data storage register B 7 ... Address register read line 8a: Storage unit A data line 8b: Storage unit B data line 9a: Data storage register A read line 9b: Data storage register B read line 10: Data line 11: Error detection signal 12: Error correctable signal 13: Error correction end Signal 14 ... Address line 15 ... Error bit designation register 16 ... Error bit designation register read line 41 ... Signal selection circuit 42 ... Error detection circuit

Continuation of the front page (56) References JP-A-3-38752 (JP, A) JP-A-57-137948 (JP, A) JP-A-57-205900 (JP, A) JP-A-4-295700 (JP, A) JP-A-53-101953 (JP, A) JP-A-63-6648 (JP, A) JP-A-2-75039 (JP, A) JP-A-3-87950 (JP, A) 6-12342 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/16 G11C 29/00 Practical file (PATOLIS) Patent file (PATOLIS)

Claims (4)

(57) [Claims] 1. A storage area having a first address space having the same address space.
When a memory element is divided into the second memory unit, said first and second simultaneously or individually addressable addressing means addresses of the same address space of the storage unit, the same address when a memory access an address register for storing an address in the space, the first and second and the first and second data storage means for storing data read from the storage unit, the error detecting means for performing error detection of the read data When including an error bit storage means for storing the position of the error bit in the read data, an error correction means for performing correction of the error bits in the read data, said error detecting means, said first and second storage The exclusive OR for each bit of the data read from the same address of the unit is calculated, and the exclusive OR of at least one bit is “1”. Der outputs a Rutoki error detection signal
The addressing means outputs the error detection signal.
The address stored in the address register.
The address of the first storage unit individually
The error correction means, when the error detection signal is output, the first addressing means individually designated by the addressing means.
After writing inversion data for each bit of the data stored in the first data storage means at the address of the storage unit , the written inversion data is read, and the read inversion data and the first data storage are read. by comparing the pre-reversal data in means, bit values match between the inverted data and the inverted data before the one that determines that a hard error
The addressing means outputs the error detection signal.
Address, the address stored in the address register
Address of the second storage unit based on the
The error correction means outputs the error detection signal.
At the time, the address designation means individually designates the second
After writing the inverted data for each bit of the data stored in the second data storage means at the address of the storage unit , the written inverted data is read, and the read inverted data and the second data storage are read. by comparing the pre-reversal data in means, bit values match between the inverted data and the inverted data before the one that determines that a hard error
There, the error correction means, all the bits stored as an error in the error bit storage means, respectively, said first
Any one of the first and second storage units
In only In the event <br/> case in which it is determined that the hard error, as the value of the corrected bits, wherein is an error bit, the pair of the first or second data storage means data
Of the bits respond, by selecting the value of <br/> bits that are not deemed to be a hard error, also performs data correction
A memory control system , characterized in that: 2. A memory device in which a storage area is divided into two storage units, and a common address space common to the two storage units.
Upon allocation, and, the two storage units, and an address decoder assigning each said two storage units unique address space is translated from the same address space, and stores the addresses of the same address space when the memory access an address register, a data storage register includes an error detection unit including an error detection circuit and a signal selection circuit, and the error bit designation register, and a memory control unit incorporating a microcomputer, the two storage units, respectively, data when writing, corresponding to an address of the same address space addresses
Scan to is intended to store the same data, said error detection circuit, when reading data, an exclusive OR for each bit data are read out to the address in the same address space from the two storage units To perform error detection on the read data.
Ri, the signal selection circuit, when no error is intended for sending one data among data read from said two memory units as valid data, said error detection circuit, when there is erroneous Activating an error detection signal , wherein the memory control means activates the error detection signal.
Was time, stores data read from each of the two storage units in the data storage register, and stores the position of the error bit in said read data to the error bit designation register, exist outside the same address space The address decoder specifies a specific address assigned to each of the two storage units , and the address decoder determines the specific address based on the specific address and the address stored in the address register.
Address corresponding to each of the two storage units
A shall, said memory control means, said two storage units it
The address specified by the address decoder
To, for each bit of the data storage registers in the data "0"
And inversion data of "1" is written and read, and the read inversion data is compared with the data before inversion in the data storage register. As a result of the comparison, between the inversion data and the data before inversion bit values match has been made to determined that the hard error, and said memory control means, all the bits stored as an error in the error bit storage means, it
Storage unit of any one of the two storage units.
If only a hard error is determined in the data storage register, the corrected value of each bit in the data is used as the corrected value of the corresponding bit of the two data in the data storage register.
Features of bets, by selecting the value of the bit is not determined as a hard error, that the data was correct, and performs activation of the delivery and error correction enable signal and the error correction end signal correction data And a memory control system . 3. A storage area having a first address space having the same address space.
When a memory element is divided into the second memory unit, said first and second simultaneously or individually addressable addressing means addresses of the same address space of the storage unit, the same address when a memory access an address register for storing an address in the space, the first and second and the first and second data storage means for storing data read from the storage unit, the error detecting means for performing error detection of the read data When including an error correction means for performing correction of the error bits in the read data, said error detection means, exclusive of each bit of data read from the same address of said first and second storage units And outputs an error detection signal when the exclusive OR of at least one bit is "1".
The addressing means outputs the error detection signal.
The address stored in the address register.
The address of the first storage unit individually
The error correction means, when the error detection signal is output, the first addressing means individually designated by the addressing means.
After writing inversion data for each bit of the data stored in the first data storage means at the address of the storage unit , the written inversion data is read, and the read inversion data and the first data storage are read. The bit having the same value between the inverted data and the data before inversion is determined as a hard error by comparing the data before inversion in the means.
The addressing means outputs the error detection signal.
Address, the address stored in the address register
Address of the second storage unit based on the
The error correction means outputs the error detection signal.
At the time, the address designation means individually designates the second
After writing the inverted data for each bit of the data stored in the second data storage means at the address of the storage unit , the written inverted data is read, and the read inverted data and the second data storage are read. by comparing the pre-reversal data in means, bit values match between the inverted data and the inverted data before the one that determines that a hard error
The error correction means detects an error in the error detection means;
All of the determined bits are the first and the
Only one of the two storage units
And it is determined to be a hard error ,
As the value of the corrected bits is to the error bit, the first or second data storage means corresponding bi Data
Of Tsu bets, by selecting the value of the bit is not determined as a hard error, the memory control system according to claim <br/> that performs data correction. 4. A memory device in which a storage area is divided into two storage units, and the two storage units share the same address space.
Upon allocation, and, the two storage units, and an address decoder assigning each said two storage units unique address space is translated from the same address space, and stores the addresses of the same address space when the memory access comprising an address register, a data storage register, and error detection unit including an error detection circuit and a signal selection circuit, and a memory control unit incorporating a microcomputer, the two storage units, respectively, when writing data, the same address address corresponding to the address of the space
Scan to is intended to store the same data, said error detection circuit, when reading data, an exclusive OR for each bit data are read out to the address in the same address space from the two storage units line Umono der error detection of the read data taking
Ri, the signal selection circuit, when no error is intended for sending one data among data read from said two memory units as valid data, said error detection circuit, when there is erroneous Activating an error detection signal , wherein the memory control means activates the error detection signal.
Was time, stores data read from each of the two storage units in the data storage register, its said two storage units that exist outside the same address space
Der specifies the respectively specified address assigned
The address decoder activates the error detection signal.
The two storage units based on the specific address and the address stored in the address register.
And the memory control means specifies the address corresponding to each of the two storage units.
The address specified by the address decoder
To, for each bit of the data storage registers in the data "0"
And inversion data of "1" is written and read, and the read inversion data is compared with the data before inversion in the data storage register. As a result of the comparison, between the inversion data and the data before inversion The bit having the same value is determined as a hard error , and the memory control unit determines whether the error is detected by the error detection unit.
All bits is determined that an error Te, respectively, the 2
Only one of the two storage units
And it is determined to be a hard error ,
As the corrected value of each bit in the data, of the corresponding bits of the two data in the data storage register ,
By selecting the value of the bit is not determined as a hard error of the data, data correct, and is characterized in that activation is performed in the transmission of correction data and the error correction enable signal and the error correction end signal Memory control system .