JP5118718B2 - Semiconductor integrated circuit and electronic equipment - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit and an electronic device, and more particularly, in a semiconductor integrated circuit using a fuse element as a nonvolatile memory element, the reliability and authenticity of data stored in the fuse element are guaranteed. And an electronic apparatus equipped with such a semiconductor integrated circuit.

  In a conventional semiconductor integrated circuit, a fuse is used as a circuit for storing relatively small capacity data such as chip-specific identification data (hereinafter referred to as a unique ID), security-related data, and memory redundancy repair information. Devices are widely used. As such a fuse element, there are an electrically rewritable electric fuse and antifuse, a laser fuse rewritable by a laser beam, and the like as memory elements that can be rewritten only once.

  A memory using a fuse element as a memory element is called “One Time Programmable-Read Only Memory” and is configured to store a value by physically cutting or destroying the fuse element and switching the conduction state to the non-conduction state. Has been. For this reason, it is difficult to restore a fuse element once cut or destroyed, and a memory using the fuse element as a memory element becomes a memory circuit having irreversibility.

  On the other hand, the data stored in the fuse element is used for various purposes, but in applications such as secure information such as unique IDs, not only data reliability but also data falsification prevention measures are taken to ensure data authenticity. There is a need to.

  As a countermeasure against this problem, as a well-known technique, a message authentication code (Message Authentication Code, hereinafter referred to as MAC) using a one-way hash function (for example, Secure Hash Algorithm (hereinafter referred to as SHA)) or a cryptographic technique is used. ) And the like are added to the stored data to ensure the reliability and authenticity of the data.

  FIG. 3 is a diagram for explaining a conventional semiconductor integrated circuit having a secure information memory.

  A semiconductor integrated circuit (semiconductor chip) 200 shown in FIG. 3 has a memory 200a that stores secure information such as a unique ID. The memory 200a stores a first storage circuit 201 that stores storage data as secure information, and verification data obtained by performing a cyclic redundancy check (hereinafter referred to as CRC) operation on the storage data. And a second memory circuit 202.

  In the semiconductor integrated circuit 200, the storage data stored in the first storage circuit 201 is verified by the verification data stored in the second storage circuit 202 by the CPU 205 mounted on the semiconductor integrated circuit.

  Patent Document 1 discloses a technique that uses a check bit for CRC calculation as check data.

JP 2008-10549 A

  However, the prior art has the following problems.

  For example, when a hash function SHA is used as inspection data, the number of bits of inspection data is 160 bits for SHA-1 and 256 bits for SHA-256. Further, when the Advanced Encryption Standard encryption is used in the MAC using the encryption technique, the number of bits of the inspection data is 128 bits or more although it depends on the bit length of the common secret key.

  In general, in the case of a unique ID used for a semiconductor integrated circuit or the like, at most about 80 bits of data such as a lot number, chip coordinates (position on a wafer), manufacturing date, manufacturing information, etc. as chip identification data Can be stored. In addition, when storing small-capacity data for various purposes, the conventional technique requires inspection data that is larger than the target data (that is, data to be stored), which increases the circuit scale of the storage circuit. there were.

  Furthermore, in order to perform data verification, a memory for storing an inspection program and software processing by the CPU are required, and verification processing time is required. Moreover, in order to shorten the verification process, it is necessary to provide a dedicated circuit, which further increases the circuit scale.

  On the other hand, as a method for solving the above problem, Patent Document 1 discloses a technique that uses a check bit of CRC calculation as check data. When CRC calculation is used as a countermeasure against data falsification, the number of bits of inspection data is 16 bits for CRC-16 and 7 bits for CRC-7. Also, the inspection circuit can be made relatively small, and the verification processing time can be made relatively short.

  However, the method of using the check bit of the CRC operation as the check data is difficult to guarantee the authenticity of the data by falsification even if the data corruption due to the failure is detected and the reliability of the data can be guaranteed. Is widely known.

  In other words, rewriting the CRC check data together with the target data (stored data) causes a data collision (a phenomenon in which the CRC value is the same even if the data contents are different), and the data is a value that has been stored correctly. Or whether the value is a falsified value.

  However, since it is a non-volatile memory circuit using a fuse element having irreversibility, it is difficult to restore a physically cut or destroyed one, so that all data cannot be freely rewritten. Therefore, although the possibility of data collision is reduced, it can be said that the authenticity of the data cannot be guaranteed because tampering may not be prevented.

  The present invention has been made to solve the above-described problems, and does not increase the circuit scale of the storage circuit and the verification circuit, and does not increase the processing time of data verification. An object of the present invention is to obtain a semiconductor integrated circuit capable of ensuring the reliability and authenticity of the semiconductor device and an electronic apparatus equipped with such a semiconductor integrated circuit.

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a nonvolatile memory circuit that irreversibly stores specific data indicating information to be stored, and the nonvolatile memory circuit is non-inverted data of the specific data. A first storage circuit that stores data, a second storage circuit that stores inverted data of the specific data, a non-inverted data of the specific data stored in the first storage circuit, and the second have a comparison circuit for comparing the inverted data of the specific data stored in the storage circuit, the comparator circuit, the non-inverted data of the specific data stored in the first memory circuit said If the inverted data of the specific data stored in the second storage circuit is inverted data, it is determined that the specific data is stored correctly in the semiconductor integrated circuit and stored in the first storage circuit. The special feature If the non-inverted data of the data is not inverted data of the inverted data of the specific data stored in the memory circuit of the second is intended determines that the specific data is not stored correctly in the semiconductor integrated circuit Yes, and the above objective is achieved.

  According to the present invention, in the semiconductor integrated circuit, the specific data is preferably composed of a plurality of bits.

  In the semiconductor integrated circuit according to the present invention, each of the first and second memory circuits has a number of fuse elements equal to the number of bits of the specific data, and the first memory circuit and the second memory circuit In the memory circuit, it is preferable that the fuse element corresponding to each bit of the specific data is complementarily cut according to the value of each bit of the specific data.

  According to the present invention, in the semiconductor integrated circuit, the fuse elements constituting the first and second memory circuits are preferably formed of a polysilicon layer formed on a semiconductor substrate via an insulating film.

  According to the present invention, in the semiconductor integrated circuit, each of the plurality of fuse elements constituting the first and second memory circuits is blown by a switch circuit provided for each fuse element. Is preferably supplied.

  According to the present invention, in the semiconductor integrated circuit, the fuse elements constituting the first and second memory circuits are preferably formed of a metal layer formed on a semiconductor substrate via an insulating film.

  According to the present invention, in each of the semiconductor integrated circuits, each of the plurality of fuse elements constituting the first and second memory circuits is at least on the surface thereof so that an energy beam for fusing the fuse elements is irradiated. It is preferable that a part is exposed.

  According to the present invention, in the semiconductor integrated circuit, the plurality of fuse elements constituting the first and second memory circuits are antifuse elements, and the antifuse element is a switch circuit provided for each antifuse element. Therefore, it is preferable that a current for conducting the antifuse element is supplied.

  In the semiconductor integrated circuit, the specific data includes a plurality of bits, and the comparison circuit includes a plurality of exclusive OR circuits corresponding to each bit of the specific data, and the plurality of exclusive ORs. AND circuit that takes the logical product of the outputs of the circuit, and each of the plurality of exclusive OR circuits has a value of a bit corresponding to non-inverted data of the specific data stored in the first storage circuit And the value of the corresponding bit of the inverted data of the specific data stored in the second memory circuit are preferably input.

  The electronic device according to the present invention is an electronic device including the above-described conductor integrated circuit of the present invention, and thereby the above-described object is achieved.

  Next, the operation will be described.

  In the present invention, the semiconductor integrated circuit includes a non-volatile memory circuit that irreversibly stores specific data indicating information to be stored, and the non-inverted data of the specific data is stored in the non-volatile memory circuit. And the second memory circuit for storing the inverted data of the specific data, when the data stored in the memory circuit is to be rewritten, due to the irreversibility of the memory circuit, the first and One of the second storage circuits prevents rewriting of stored data. This ensures the reliability and authenticity of the stored data.

  Further, since the non-inverted data of the specific data is stored in the first memory circuit and the inverted data of the specific data is stored in the second memory circuit, the verification of the specific data is performed for each bit of the specific data. In addition, by comparing the non-inverted data with the inverted data, it can be performed in a short time with a logic circuit having a simple configuration.

  As described above, according to the present invention, a semiconductor integrated circuit includes a non-volatile storage circuit that irreversibly stores specific data indicating information to be stored, and the non-inversion of the specific data Since the first memory circuit that stores data and the second memory circuit that stores the inverted data of the specific data are used, the memory circuit can be verified by using the irreversibility of the nonvolatile memory circuit. There is an effect that the reliability and authenticity of the stored data can be ensured without enlarging the circuit scale of the circuit and without increasing the data verification processing time.

FIG. 1 is a diagram for explaining a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 1 (a) shows a semiconductor chip as the semiconductor integrated circuit, and FIG. 1 (b) shows the semiconductor chip. The structure of the mounted non-volatile memory is shown. FIG. 2 is a diagram for specifically explaining the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2A shows an electric fuse element constituting the nonvolatile memory, and stored data and verification data. FIG. 2B shows an example of an electric fuse element, and FIG. 2C shows a configuration of an output unit of a memory circuit using the electric fuse element. FIG. 3 is a diagram for explaining a semiconductor integrated circuit equipped with a conventional non-volatile memory storing secure information. FIG. 3A shows a semiconductor chip as the semiconductor integrated circuit, and FIG. Shows the configuration of the nonvolatile memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 1 (a) shows a semiconductor chip as the semiconductor integrated circuit, and FIG. 1 (b) shows the semiconductor chip. The structure of the mounted non-volatile memory is shown.

  FIG. 2 is a diagram for specifically explaining the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 2A shows an electric fuse element constituting the nonvolatile memory, and stored data and verification data. FIG. 2B shows an example of an electric fuse element, and FIG. 2C shows a configuration of an output unit of a memory circuit using the electric fuse element.

  The semiconductor integrated circuit 100 according to the first embodiment includes a nonvolatile memory (nonvolatile memory circuit) 100a that irreversibly stores specific data indicating information to be stored. Here, the specific data is identification data unique to the chip (hereinafter referred to as a unique ID), security-related data, and data related to memory redundancy repair information. In particular, the unique ID is a lot number or chip identification data. It shows chip coordinates (position on the wafer), manufacturing date, manufacturing information, and the like.

  The non-volatile memory 100a includes a first storage circuit 101 that stores non-inverted data of the specific data, and a second storage circuit 102 that stores inverted data of the specific data. The specific data is composed of a plurality of bits, preferably about 40 to 50 bits. Each of the first and second memory circuits 101 and 102 has a number of fuse elements 106 and 107 equivalent to the number of bits of the specific data, and the first memory circuit 101 and the second memory circuit In the circuit 102, the fuse element corresponding to each bit of the specific data is complementarily cut according to the value of each bit of the specific data.

  Here, the non-inverted data of the specific data stored in the first storage circuit 101 is the target data (storage data) 103 to be stored, and the inverted data of the specific data stored in the second storage circuit 102 Is data (verification data) 104 obtained by logically negating the target data to be stored.

  In addition, as shown in FIG. 2B, the fuse elements constituting the first and second memory circuits connect opposite electrodes 12 formed on the semiconductor substrate 10 with an insulating film 11 interposed therebetween. It consists of a polysilicon layer 20. The polysilicon layer 20 is formed on the insulating film 13. Each fuse element is supplied with a current for fusing the fuse element by a switch circuit (not shown) provided for each fuse element.

  The output unit 107 corresponding to each bit of the first memory circuit 101 includes, for example, a P-type transistor 107a and a fuse circuit 107b connected in series between the power source and the ground, as shown in FIG. The storage data can be output from a connection point between the transistor element 107a and the fuse circuit 107b. Here, the fuse circuit 107b includes the fuse element 106 shown in FIG. In addition, the output unit corresponding to each bit of the second memory circuit 102 can be configured similarly to the output unit 107 corresponding to each bit of the first memory circuit.

  The fuse elements constituting the first and second memory circuits are not limited to the polysilicon layer 20 and may be constituted by a metal layer formed on the semiconductor substrate via an insulating film. In this case, it is desirable that the fuse element has a structure in which at least a part of the surface thereof is exposed so that an energy beam such as a laser beam for fusing the fuse element is irradiated.

  Further, the fuse element is not limited to an electric fuse that is cut by application of current, but may be an antifuse element that changes to a conductive state by application of current. In this case, the semiconductor integrated circuit is preferably configured such that a current for making the antifuse element conductive is supplied to the antifuse element by a switch circuit provided for each antifuse element.

  Furthermore, the semiconductor integrated circuit 101a of this embodiment includes non-inverted data 103 of specific data stored in the first storage circuit 101, and inverted data 104 of specific data stored in the second storage circuit 102. A data comparison (verification) unit (comparison circuit) 105 is provided.

  Specifically, the data comparison verification unit 105 includes a plurality of exclusive OR circuits 108 corresponding to each bit of specific data, and an AND circuit 109 that performs a logical product of outputs 110 of the plurality of exclusive OR circuits. Each of the plurality of exclusive OR circuits 108 includes a value of a bit corresponding to non-inverted data of specific data stored in the first storage circuit 101 and the second storage circuit 102. And the value of the corresponding bit of the inverted data of the specific data stored in.

  In the above description, the number of fuse elements in the first and second memory circuits is equal to the number of bits of the specific data, but the number of fuse elements in the first and second memory circuits is It does not have to be the same as the number of bits of the specific data, and may be larger than that. For the remaining fuse elements, a predetermined value that is not related to the specific data may be set.

  Next, the function and effect of the present invention will be described.

  The target data (non-inverted data of specific data) 103 is stored in the first memory circuit 101 using the fuse element 106. Similarly, inspection data (inverted data of specific data) 104 is stored in the second memory circuit 102 using the fuse element 107. In the inspection data 104, a value (inverted data) logically negated with the same number of bits as the target data 103 is set. Each storage circuit stores a value by physically cutting or destroying the fuse element by a method suitable for various fuse elements.

  The target data 103 is read from the storage circuit 101 and used for various purposes. The target data 103 is compared with the inspection data 104 by a data comparison (verification) unit 105 to verify whether the data is stored correctly. As described above, the inspection data 104 is a logically negated value of each bit of the data 103. If the data is stored correctly, all corresponding bits have different values.

  If the target data 103 or the inspection data 104 has been garbled due to the influence of dust or foreign matter, the corresponding bits have the same value, and the data comparison (verification) unit 105 has garbled the data. Judging. This determination can be easily made by a simple circuit configured by software processing based on a basic CPU instruction or exclusive OR of each bit.

  Further, in this way, let us try to tamper with the specific data in which the non-inverted data 103 of the specific data is stored in the first storage circuit 101 and the inverted data 104 of the specific data is stored in the second storage circuit 102. Then, it is necessary to change both the target data 103 and the verification data 104 so that no error occurs in the data comparison verification.

  For example, when a certain bit of target data is changed from “1” to “0”, the corresponding verification data bit needs to be changed from “0” to “1”. However, as described above, since the nonvolatile memory circuit using the fuse element is physically cut or broken, it is possible to program in one direction but it is difficult to program in the reverse direction. Therefore, the authenticity of the data is guaranteed by utilizing the irreversibility of the fuse element.

  In the present invention, the circuit for storing the target data 103 and the inspection data 104 may be a single memory circuit or a plurality of memory circuits as long as the data group can be stored.

  Next, a more specific operation will be described by taking as an example the case where an electric fuse is used as a fuse element.

  For example, the value of the electric fuse 106 in the initial state is set to “0”, and the value of the electric fuse 107 in the non-conductive state due to cutting or breaking is set to “1”. At this time, the electric fuse can be written from the value “0” to the value “1”, but it may be difficult to restore the non-conducting value “1” to the value “0” in the reverse direction. Recognize.

  Next, as an example, assuming that the data length to be stored is 6 bits and the stored data (specific data) 103 is the non-inverted data “010100”, the inspection data 104 is the inverted data of the specific data that is the logical negated data of each bit. 6 bits of 1010111 ″ are stored.

  In order to verify whether the data is correctly stored when the stored data 103 is used by a CPU or the like, the outputs 110 of the plurality of exclusive ORs 108 in the data comparison (verification) unit 5 are used. The stored data 103 is compared with the inspection data 104 for each bit. Since the corresponding bits are inverted values of “0” and “1”, the data comparison result 110 that is the output of the exclusive OR circuit 108 of each bit is “111111”, and these signals are The output 111 of the combined logical product circuit (AND circuit) 109 becomes “1”. That is, when the final data comparison result 111 is “1”, it can be determined that the data is stored correctly.

  On the other hand, when the final data comparison result 111 is “0”, any value of the data comparison result 110 of the exclusive OR circuit 108 is “0”. For example, if the least significant bit of the target data 103 is garbled from “0” to “1”, the data 103 is “010101” and the verification data 104 is “101011”. The data comparison result 110 in the circuit 08 is “111110”. At this time, the final data comparison result 111 is “0”, a data error can be detected, and it can be determined that data is not stored correctly. By such a verification method, the reliability of data is guaranteed.

  Next, as an explanation for guaranteeing the authenticity of data, consider a case where the target data 103 is falsified from “010100” to “010101”.

  For example, if the least significant bit of the storage data 103 intended for data falsification is changed from “0” to “1”, this is the same as data corruption in the verification of data reliability, and the final data comparison result 111 is “0” and a data error is detected. Therefore, in order to prevent a data error, it is necessary to tamper the least significant bit of the verification bit from “1” to “0”. That is, if the verification data 104 can be changed to “101010”, the falsified data 103 is “010101” that is stored correctly. However, as described above, the change from “1” to “0” is a change from a non-conducting state of physical disconnection or destruction to a conducting state, and since it is actually very difficult to restore, the authenticity of the data Is guaranteed.

  As described above, in the first embodiment of the present invention, the non-inverted data of the specific data is stored as the target data and the logical negation data of the target data as the inspection data in the semiconductor integrated circuit 100 using the fuse element as the storage element. By storing (inverted data of specific data) and utilizing the irreversibility of the fuse element, without increasing the circuit scale of the storage circuit and the verification circuit, and without increasing the data verification processing time, An effect of ensuring the reliability and authenticity of the stored data can be obtained.

  Furthermore, the semiconductor integrated circuit 100 of the first embodiment is suitable not only as a mobile device such as a mobile phone, a portable game device, and a notebook personal computer but also as a semiconductor chip constituting various electronic devices. 100 can be used reliably as a semiconductor chip constituting these electronic devices.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. It is understood that the patent documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  In the field of a semiconductor integrated circuit using a fuse element as a non-volatile storage element and an electronic apparatus equipped with such a semiconductor integrated circuit, the present invention provides non-inverted data of target specific data and an object as inspection data. By storing the inverted data (logical negation data) of the specific data to be used and utilizing the irreversibility of the fuse element, it is possible to increase the processing time of data verification without increasing the circuit scale of the storage circuit and the verification circuit. The reliability and authenticity of stored data can be ensured without incurring.

101 First storage circuit (storage circuit for target storage data)
102 Second storage circuit (inspection data storage circuit)
103 Target data 104 Inspection data (inverted data of target data)
105 Data Comparison (Verification) Unit 106 Fuse Element (Conductive State)
107 Fuse element (non-conductive state)
108 exclusive OR sea route (XOR circuit)
109 Logical product route (AND circuit)
110 Data comparison result (exclusive OR output)
111 Final data comparison result (logical product output)

Claims (10)

A semiconductor integrated circuit having a nonvolatile memory circuit that irreversibly stores specific data indicating information to be stored,
The nonvolatile memory circuit includes:
A first storage circuit for storing non-inverted data of the specific data;
A second storage circuit for storing inverted data of the specific data;
And the non-inverted data of the specific data stored in the first storage circuit, a comparison circuit for comparing the inverted data of the specific data stored in the second storage circuit possess,
The comparison circuit
In the semiconductor integrated circuit, when the non-inverted data of the specific data stored in the first memory circuit is the inverted data of the inverted data of the specific data stored in the second memory circuit It is determined that the specific data is stored correctly,
When the non-inverted data of the specific data stored in the first memory circuit is not the inverted data of the inverted data of the specific data stored in the second memory circuit, the semiconductor integrated circuit A semiconductor integrated circuit that determines that specific data is not stored correctly . The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein the specific data comprises a plurality of bits. The semiconductor integrated circuit according to claim 2,
Each of the first and second memory circuits has a number of fuse elements equal to the number of bits of the specific data,
In the first memory circuit and the second memory circuit, a fuse element corresponding to each bit of the specific data is complementarily cut in accordance with the value of each bit of the specific data. circuit. The semiconductor integrated circuit according to claim 3,
The fuse element constituting the first and second memory circuits is a semiconductor integrated circuit comprising a polysilicon layer formed on a semiconductor substrate via an insulating film. The semiconductor integrated circuit according to claim 4,
Each of the plurality of fuse elements constituting the first and second memory circuits includes:
A semiconductor integrated circuit in which a current for blowing the fuse element is supplied by a switch circuit provided for each fuse element. The semiconductor integrated circuit according to claim 3,
The fuse element constituting the first and second memory circuits is a semiconductor integrated circuit comprising a metal layer formed on a semiconductor substrate via an insulating film. The semiconductor integrated circuit according to claim 4,
Each of the plurality of fuse elements constituting the first and second memory circuits is
A semiconductor integrated circuit in which at least a part of the surface is exposed so that an energy beam for fusing the fuse element is irradiated. The semiconductor integrated circuit according to claim 3,
The plurality of fuse elements constituting the first and second memory circuits are antifuse elements,
The antifuse element is a semiconductor integrated circuit in which a current for making the antifuse element conductive is supplied by a switch circuit provided for each antifuse element. The semiconductor integrated circuit according to claim 1,
The specific data consists of a plurality of bits,
The comparison circuit
A plurality of exclusive OR circuits corresponding to each bit of the specific data;
An AND circuit that takes a logical product of outputs of the plurality of exclusive OR circuits,
Each of the plurality of exclusive OR circuits includes a value of a bit corresponding to non-inverted data of the specific data stored in the first storage circuit and specific data stored in the second storage circuit. A semiconductor integrated circuit having as input the value of the corresponding bit of the inverted data. An electronic apparatus comprising the semiconductor integrated circuit according to claim 1.

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