JP3341745B2 - Electronic disk drive write / read control method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write / read control method and apparatus for an electronic disk device, and more particularly, to a write / read method for an electronic disk device suitable for effectively utilizing a semiconductor memory element used as a storage device. The present invention relates to a control method and an apparatus therefor.

[0002]

2. Description of the Related Art As semiconductor memory devices have become more highly integrated, semiconductor memory devices that exceed the storage capacity of magnetic disk devices of a long time ago have been manufactured at low cost. For this reason, instead of a conventional magnetic disk drive, for example, a dynamic random access memory (DRAM)
2. Description of the Related Art An electronic disk device using a semiconductor storage element such as a flash memory or a flash memory as a storage device for storing data has become widespread.

[0003] Electronic disk devices have the advantage of being able to access at high speed and have no mechanical moving parts, but are more expensive than magnetic disk devices in terms of unit price per storage capacity. . Therefore, when data is stored in an electronic disk device, various methods for effectively utilizing the storage capacity have been proposed and applied.

When data is stored in a memory, the data may have a vertical parity, a horizontal parity, or a cyclic code (CR).
Error detection code such as C: Cyclic Redundancy Check) and error correction code (ECC: Error Correction Code)
Is generally stored in a memory. The error correction code requires a larger number of bits as the error correction capability is increased. The longer the data length of the digital data to be corrected, the larger the number of bits.

Conventionally, to reduce the number of bits of the error correction code so that more data can be stored in a memory, data is divided as shown in FIG. Is stored separately. In FIG. 3, data [D ₀₀ D _{0 1] of} one word (data width processed when accessing the DRAM)
D ₀₂ ...] _Are divided for each bit, and the next word data [D ₁₀ D ₁₁ D ₁₂ .
Then, the first bits D ₀₀ , D ₁₀ ,... Of each word are stored in the first DRAM, and the second bits D ₀₁ , D ₁₁ ,.
Are stored in the second DRAM, and... Are stored in separate DRAMs one bit at a time, thereby reducing the number of bits of the required error correction code.

[0006] Incidentally, as related to the prior art, there is one described in Japanese Patent Application Laid-Open No. Hei 10-214235.

[0007]

An error correction code (EC) stored in a semiconductor memory element as in the above-mentioned prior art is used.
The memory consumption can be reduced by reducing the number of bits in C). However, according to this conventional method, the minimum number of transfers when writing data to the semiconductor storage element is 1 word length × the number of bits of the DRAM.

On the other hand, in a storage area (disk area) in which a semiconductor storage element is used as a disk device, data is managed and stored in sector units as in a magnetic disk device. For this reason, data whose data amount exceeds one sector (usually 256 bytes or 512 bytes) by even one bit consumes two sectors of memory.

In the electronic disk device, when a failure occurs in a higher-level device and data transfer is interrupted halfway, the above-described error detection code (hereinafter, referred to as CRC) is inverted and written into a semiconductor memory element, and this CRC is written. By checking, it is determined whether or not the data is a destructive write. This CRC usually has a data amount of 2 bytes, and when data obtained by adding CRC to data of one sector is stored in the semiconductor memory element, memory of two sectors is consumed.

At this time, in order to create an ECC also for CRC data, as shown in FIG. 4, extra data (for example, data of only "0") is added to the CRC.
It must be stored in a semiconductor storage element. In this,
There is a problem that a data transfer load is large and a valuable memory area of the semiconductor storage element is wastefully consumed and cannot be used efficiently.

An object of the present invention is to provide a write / read control method and an apparatus for an electronic disk device that reduce the data transfer load and efficiently use the memory area.

[0012]

Means for Solving the Problems In order to solve the above problems,
According to the write / read control method for an electronic disk device of the present invention, in the write / read control method for an electronic disk device that stores and reads data in a semiconductor memory element in sector units, whether there is an abnormality in data transferred from a higher-level device Whether the data is correct or not is identified by an error detection code added to the data, a check bit indicating normal / abnormal indicating the identification result is stored in the semiconductor memory element corresponding to the data, and an error detection code is added to the data. Instead, the data is stored in a disk area of the semiconductor storage element.

According to a write / read control method for an electronic disk device of the present invention, when data is read from a disk area of a semiconductor memory device, the check bit corresponding to the data is checked, and whether the data is normal or abnormal is determined by a host device. It is characterized by notifying.

Further, the write / read control method for an electronic disk device according to the present invention is characterized in that the check bit has a structure in which two bits of a bit indicating normal / abnormal and an inverted bit thereof are duplicated.

Further, the write / read control device of the electronic disk device of the present invention stores and reads data in the semiconductor memory element in sector units, and determines whether or not the data transferred from the host device has an abnormality. A check bit indicating normal / abnormal indicating the identification result, which is identified by the error detection code added to the data, is stored in the semiconductor memory element corresponding to the data, and the data is stored in the semiconductor memory without adding the error detection code to the data. It is characterized by comprising means for storing data in a disk area of the semiconductor storage element.

Further, the read / write control device of the electronic disk device of the present invention, when reading data from the disk area of the semiconductor storage element, checks the check bit corresponding to the data and determines whether the data is normal or abnormal. Is provided.

Further, the write / read control device for an electronic disk device according to the present invention is characterized in that the check bit has a structure in which two bits, a bit indicating normal / abnormal and an inverted bit thereof, are duplicated.

Further, the electronic disk device of the present invention is connected to a write / read control device and is provided with a storage area for storing the check bit.

That is, an object of the present invention is to add, in a write / read control of an electronic disk device for storing and reading data to and from a semiconductor storage element in units of a sector, to the data transferred from a higher-order device whether the data is abnormal or not. A check bit indicating normality / abnormality indicating the identification result is stored in the semiconductor memory element corresponding to the data, and the data is stored in the semiconductor memory without adding an error detection code to the data. This is achieved by storing in the disk area of the storage element.

Further, the above object is attained by reading the check bit corresponding to the data when reading data from the disk area of the semiconductor memory device and notifying the host device of the normal / abnormal of the data.

With this configuration, when data is stored in the semiconductor memory element without storing a CRC, the storage area can be saved and the number of data transfers can be reduced. it can. Instead of not adding a CRC, a check bit indicating normal / abnormal data is provided, so that the reliability of the data does not change.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a write / read control device of an electronic disk device according to an embodiment of the present invention. The write / read control device is provided between the host device 1 and the semiconductor storage element 2 of the electronic disk device, takes in data transferred from the host device 1, and checks a CRC of the data. An ECC generation circuit 4 for generating an ECC for the data checked by the CRC check circuit 3 and adding the ECC to the data and storing the same in the semiconductor memory element 2, and a check bit generation circuit 5 and a check circuit 6 described in detail later Equipped.

As described with reference to FIG. 3, data stored in the semiconductor memory element 2 is divided into data of one word one bit at a time and separated into separate semiconductor memory elements 2 or separate data together with data of other words. Stored in the disk area, EC
The number of C bits is reduced. In the present invention, the data to be stored in the semiconductor storage element 2 on a sector-by-sector basis does not include a CRC as in the related art. Instead, a check bit is generated as described later, and this is stored in another area other than the disk area or in another semiconductor storage element in correspondence with the data written from the ECC generation circuit 4 to the semiconductor element 2. Hereinafter, the check bit will be described.

The CRC check circuit 3 checks the CRC of the data transferred from the host device 1 and identifies whether the data is normal or abnormal data in which a failure has occurred during data transfer. Then, the identification result is sent to the check bit generation circuit 5.

The check bit generation circuit 5 sets a predetermined parity bit, for example, “1” for each data of the above minimum transfer number when the identification result is “normal”, and inverts the parity bit by one bit. Is set, and the 2-bit data '10' is stored in one semiconductor storage element 2 as a check bit. In the present embodiment, in order to improve the reliability of the check bit, the check bit is duplicated, and the check bit is stored in another semiconductor memory element 2.

The check bit generation circuit 5 receives the identification result of "abnormal" from the CRC check circuit 3 with respect to the data of the minimum transfer number, and performs a check in which the "normal" check bit is inverted. Make a bit.
In the above example, since "10" was a normal check bit, "01" is set as an abnormal check bit, which is duplicated, and this abnormal check bit is stored in a semiconductor memory in response to the above abnormal data subjected to destructive writing. Stored in element 2.

The upper part of FIG. 2 is a conceptual diagram of the check bit generation circuit 5 described above. As described above, the check bit generation circuit 5 sets a predetermined parity bit at the signal terminal A when the data is “normal”. In the above example, "1" is set. As a result, the lower bits inverted by the inverter 7a (7b) are added, and two check bits of '10' are written in the two semiconductor storage elements 2a and 2b, respectively.

When data is read from the semiconductor memory device 2 of FIG. 1, the data and ECC stored in the disk area and the above-mentioned check bit are read,
The data is transferred to the host device 1 through the check circuit 6. At this time, the check circuit 6 determines the check bit and, if the data is destructively written abnormal data, notifies the host device 1 of the fact.

The lower side of FIG. 2 is a conceptual diagram of the check circuit 6. When the check bit read from the semiconductor storage element 2a (2b) is "10" indicating "normal", the lower bits are inverted by the inverter 8a (8b), and the comparator 9a (9b) outputs " 11 'is input, and since both bits are' 1 ',' 1 'is output. This allows
'11' is also input to the comparator 10, and '1' indicating "normal" is output from the comparator 10 to the signal terminal B.

Similarly, when the parity bit of "0" indicating "abnormal" is set at the signal terminal A because it is destructive write data, "01" is written to the semiconductor memory elements 2a and 2b and read. The check circuit 6 outputs “0” indicating “abnormal” to the signal terminal B.

As described above, a CRC is added to data in order to determine whether or not a destructive write has been made, not only by a parity bit indicating normal / abnormal, but also by a 2-bit check bit in combination with the inverted bit. Without this, it is possible to determine the destructive writing with high reliability. In addition, since the two check bits are further duplicated, the reliability is further improved.

[0032]

According to the present invention, data to which CRC is not added is stored in the disk area of the semiconductor memory device.
While that memory area can be used effectively,
This has the effect of reducing the number of data transfers and the transfer load.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an electronic disk write / read control device according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram of a check bit generation circuit and a check circuit shown in FIG.

FIG. 3 is a diagram illustrating an example of a technique for dividing and storing data in a plurality of DRAMs to reduce the number of ECC bits;

FIG. 4 is an explanatory diagram of a case where a CRC is added to stored data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper apparatus 2 Semiconductor memory element 3 CRC check circuit 4 ECC generation circuit 5 Check bit generation circuit 6 Check circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/16 G06F 11/10 G06F 11/16 G06F 3/08

Claims (7)

(57) [Claims] In a write / read control method of an electronic disk device for storing and reading data in a semiconductor memory element in sector units, it is added to a data transferred from a host device whether or not there is an abnormality. A check bit indicating normal / abnormal indicating the identification result is stored in the semiconductor storage element corresponding to the data, and the data is stored in the semiconductor storage element without adding an error detection code to the data. A write / read control method for an electronic disk device, wherein the read / write control method is stored in a disk area. 2. The write / read control method for an electronic disk device according to claim 1, wherein when data is read from a disk area of the semiconductor storage element, the check bit corresponding to the data is checked to determine whether the data is normal or abnormal. Control method for notifying the host device of the write / read of the electronic disk device. 3. The write / read control method for an electronic disk device according to claim 1, wherein the check bit has a configuration in which two bits, a normal / abnormal bit and an inverted bit thereof, are duplicated. A method for controlling writing / reading of an electronic disk device, characterized in that: 4. A writing / reading control device of an electronic disk device for storing and reading data in a sector unit in a semiconductor memory element, wherein whether or not data transferred from a host device has an abnormality is added to the data. A check bit indicating normality / abnormality which is identified by an error detection code and which indicates the identification result is stored in the semiconductor memory element corresponding to the data, and the data is stored in the semiconductor memory element without adding an error detection code to the data. A write / read control device for an electronic disk device, comprising means for storing data in a disk area. 5. The read / write control device for an electronic disk device according to claim 4, wherein when the data is read from the disk area of the semiconductor storage element, the check bit corresponding to the data is inspected and the data is checked for normal / abnormal. A read / write control device for an electronic disk device, comprising means for notifying the host device of the above. 6. The write / read control device for an electronic disk device according to claim 4, wherein the check bit has a configuration in which two bits of a bit indicating normal / abnormal and an inverted bit thereof are duplicated. A writing / reading control device for an electronic disk device. 7. An electronic disk device connected to the write / read control device according to claim 4, wherein a storage area for storing the check bit is provided. Electronic disk device.