JPS58200351A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To transfer input information at a high speed and to transfer error correcting information, by providing an error correcting means capable of using an input and an output information line in common, and a means of holding the input information except a check bit. CONSTITUTION:The input information is supplied to a common input/output information line 101, selected by selection control circuits 101 and 1-2, and sent to data control circuits 2-1 and 2-2 of an error correcting circuit 2. An error correcting code is added after an error check and the resulting information is stored in a memory module 4 through a selecting circuit 1-2. Information read out of the module is held in a circuit 3 through a selecting circuit 1, selected by a circuit 1-5, and sent to an external device through the information line 101. At the same time, it is sent to the circuits 2-1 and 2-2 through the circuits 1-1 and 1-3 to make an error check. If an error is found, the information is sent to the external device through an information line 102 and if the error is correctable, the information is sent out to the external device through the information line 101 after the error is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for correcting errors in transferred information used in computers and the like.

In general, many storage devices are equipped with an error correction function that detects and corrects errors in memory read information in order to increase the reliability of the device. As an example of such a garbled correction circuit for a storage device, a conventional example capable of performing 1-bit error correction and 2-bit error detection using a Hamming code will be described with reference to the block diagram of FIG. In this figure, information input from an input information line 1 is held in an information holding circuit 2.

It is added to the information selection circuit 3 connected to the output side, and selection with write information to be described later is performed. Information selection circuit 3
The output is given to the No-Mink code generation circuit 4, where a Hamming code is generated, and then input to the write information holding circuit 5 together with the output of the information selection circuit 3, where it is held. The output of the write information holding circuit 5 is written into the memory module 6 under the control of signals applied via the memory module control line 12 and address signal line 13.

Next, at the time of reading, the address signal line 13 and the memory module control line 12 are connected to the memory module 6.
The stored information is read out under control via the error correction circuit 7 and is applied to the read information holding circuit 7-1 of the error correction circuit 7 and held therein. The output of the read information holding circuit 7-j is applied to the Hamming code decoding circuit 7-2, the Hamming code is decoded, and the output is input to the error correction circuit 7-3 together with the information of the holding circuit 7-1. Any errors in the information provided will be corrected here. Error correction circuit 7-3
The output is output as read information to an external device (not shown) through an information line 8. The control lines 9, 10 and 11 are control lines for outputting information from the information holding circuits 2, 7-1 and 5, respectively.

By the way, according to such a conventional example, the information read from the memory module 6 is always corrected by the Hamming code decoding circuit 7-2 and the error correction circuit 7-3 before being output. The probability that a read error will occur in an actual storage device is small, and in most cases, it results in wasted time. Therefore, when high-speed reading is required in the storage device, the read information from the memory module 6 held in the read information holding circuit 7-1 is directly output in advance to an external device. And if there is an error in this read information.

Thereafter, the existence of an error is notified to an external device, and the reading information corrected by the Scherer code is outputted by the above-mentioned no-ming code decoding circuit and error correction circuit. The broken line leader line shown in the figure is a read information output line for outputting read information from the memory 6. However, due to recent demands for high-speed processing, economy, and miniaturization, when trying to implement LSI in error correction circuits,
Due to the limit on the number of LSI bins, there remains the problem that it is not possible to draw out the output line for the above-mentioned memory read information.

purpose of invention The object of the present invention is to solve the problems of the prior art.

By providing an error correction means that can commonly use an input information line and an output information line, and a means for holding input information excluding check pits.

An object of the present invention is to provide an error correction circuit suitable for LSI implementation, which enables high-speed a'''m' + input information and transfers error correction information when a - error exists in the information.

Features of the Invention According to the present invention, in an error correction circuit that corrects errors in a plurality of pieces of information when transferring these pieces of information in parallel, input information including a check pit for error correction and output information after error correction are corrected. an error correction means inputting and outputting via a common information line; a means for inputting and retaining information other than check pits among the input information added to the error correction means;
Receiving the output of the error correcting means and the output of the holding means.

There is obtained a transfer information error correction circuit characterized in that it includes a selection means for selecting these pieces of information and outputting the selected information to the common information line.

Next, an error correction circuit according to the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a first embodiment of the present invention. In fig.

The error correction circuit includes a data system selection circuit 1 including information selection control circuits 1-1 to 1-5, and a data control circuit 2-1゜2-.
2, and an information holding circuit 3 that receives and holds memory read information (5). Furthermore, the memory module 4 is composed of multiple memory blocks 4-1 and 4-2.

Of the above, the error correction circuit 2 includes an error check code generation circuit, an error detection circuit, and an error correction circuit in association with the data control circuits 2-1 and 2-2, respectively. Reading and writing are possible via the information line that shares input and output. The read information holding circuit 3 receives read information from the memory module 4 via the data system selection circuit 1 and holds it.

To explain the operation of the embodiment configured in this way, first, input information given to the shared input/output information line 101 is transmitted to the data system selection circuit 1 via the control line 24. or information selection control circuit 1 controlled by 22 1-1. or selected by 1-3.

Data control circuit 2-1 of error correction circuit 2. or 2-2
will be forwarded to. This input information is transferred.

After error checking is performed in the error correction circuit 2 and an error correction code is added, the data is transferred to the memory module 4 via the information selection control circuit 1-2 of the data system selection (6) circuit 1. In this memory module 4, control lines 26, 28 . Information added with an error correction code, which is transferred to memory block 4-1 or 4-2 under write control from address lines 27 and 29, is stored.

The reading of stored information in the memory module 4 is likewise carried out via control lines 26, 28 . This is done by signal control using address lines 27 and 28. The read information passes through the data system selection circuit 1.

It is held in the direct read information holding circuit 3.

Information selection control circuits 1-1 and 1-3 are provided with respective control lines 24. or 22, the multi-information selection control circuit 1-1. Or, by operating data control circuit 2-1.1-3. Or given to 2-2.

The information held in the read information holding circuit 3 first.

In the information selection control circuits 1 and -5, control of the control line 25;
- Selected by the controller and transferred to an external device (not shown) via the input/output information line 101. Further, the data control circuit 2-1. Alternatively, the information read from the memory inputted to 2-2 is checked for errors, and after error correction, if there is an error, the existence of the error is reported to the above-mentioned external device via the error information line 102'. Alternatively, if the error can be corrected, the data control circuit 2-1. or 2-
After error correction in step 2, information selection control circuit 1-
Send it to 4.

Under the control of the control line 21, read error correction information is sent to the external device via the input/output information line 101.

In the above embodiment, an example is shown in which two memory blocks are provided in the memory module and two data control circuits of the error correction circuit are shared for input/output lines, reading, and writing, respectively. It goes without saying that the numbers of memory blocks and data control circuits can be selected as desired. Also.

The information read from the memory module passes through the data system selection circuit 1 and is held in the information holding circuit 3.
It is also possible to add the signal to the information holding circuit after passing through the control circuit within the data system selection circuit.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. In this example, two memory blocks are used in the memory module 4 and two data control circuits are used in the error correction circuit 6. As in the first embodiment, the data control circuits 6-1 and 6-2 are each provided with common input/output lines, but the data control circuit 6-1 is used for reading the memory module 4. The difference from the first embodiment is that the data control circuit 6-2 is dedicated for writing. Therefore, the data system selection circuit 5 includes an information selection control circuit 5 used for selecting read information.
-1. Information selection control circuit 5-2 used for selecting write information. An information selection control circuit 5-3 for sending read information held in the information holding circuit 3 is provided. The overall operation including the information selection control circuit can be easily understood without further explanation.

Effects of the Invention As is clear from the above explanation, (1) according to the present invention, the input/output information lines of the error correction circuit are shared, (9) the number of signal lines is reduced, and the signal lines are separated from the error correction circuit. The read information is transferred through the read information holding circuit provided, and if there is an error in the read information, correction information is transferred later, thereby simplifying the configuration and making it easier to apply to LSI. , which has a great effect on improving high-speed transfer performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional example of an error correction circuit applied to a storage device, FIG. 2 is a block diagram showing the configuration of a first embodiment according to the present invention, and FIG. 3 is a block diagram showing the configuration of a first embodiment according to the present invention. FIG. 2 is a block diagram showing the configuration of a second embodiment. In the figure, 1 and 5 are data system selection circuits, 1-1 to 1-
5, 5-1 to 5-3 are information selection control circuits, 2 and 6 are error correction circuits, 2-1, 2-2, 6-1, 6-2
3 is a data control circuit, 3 is a read information holding circuit, 4 is a memory module, and 4-1 and 4-2 are memory blocks. (10)

Claims (1)

[Claims] 1. In an error correction circuit that corrects errors in multiple pieces of information when transferring them in parallel, input information including check pits for error correction and output information after error correction are input via a common information line. an error correction means for outputting, a means for inputting and holding information excluding check pits among the input information added to the error correction means, and a means for receiving the output of the error correction means and the output of the holding means; , and selecting means for selecting these pieces of information and outputting the selected information to the common information line.