JPS6312303B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit for transfer information used in computers and the like.

In general, many storage devices are equipped with an error correction function that detects and corrects errors in memory read information in order to increase the reliability of the device. As an example of such an error correction circuit for a storage device, a conventional example capable of performing 1-bit error correction and 2-bit error detection using a Hamming code will be described with reference to the block diagram of FIG. In this figure, information input from an input information line 1 is held in an information holding circuit 2, and then added to an information selection circuit 3 connected to the output side of the information holding circuit 2, where it is selected from write information to be described later. The output of the information selection circuit 3 is given to a Hamming code generation circuit 4, where a Hamming code is generated, and then inputted together with the output of the information selection circuit 3 to a write information holding circuit 5 where it is held. The output of this write information holding circuit 5 is connected to the memory module control line 1.
2 and the address signal line 13, and are written into the memory module 6. Next, at the time of reading, the information stored in the memory module 6 is read out under control via the address signal line 13 and the memory module control line 12, and the read information holding circuit 7-1 of the error correction circuit 7 given and retained. The output of the read information holding circuit 7-1 is applied to a Hamming code discontinuation circuit 7-2, the Hamming code is decoded, and the output is input to the error correction circuit 7-3 together with the information of the holding circuit 7-1. Any errors in the information provided will be corrected here. The output of the error correction circuit 7-3 is output as read information to an external device (not shown) through the information line 8. Note that control lines 9, 10, and 11 are control lines for outputting information from information holding circuits 2, 7-1, and 5, respectively.

By the way, according to such a conventional example, the information read from the memory module 6 is always sent to the Hamming code cancellation circuit 7-2 and the error correction circuit 7-3.
However, the probability that a read error will occur in an actual storage device is small, and in most cases, time is wasted. Therefore, when high-speed reading is required in the storage device, the read information from the memory module 6 held in the read information holding circuit 7-1 is directly output in advance to an external device. If there is an error in this read information, the existence of the error will be notified to the external device,
The Hamming code discontinuation circuit and the error correction circuit output error-corrected read information. The broken line leader line shown in the figure is a read information output line for outputting read information from the memory 6. However, due to recent demands for high-speed processing, economy, and miniaturization, when trying to implement LSI in error correction circuits,
Due to the limited number of LSI pins, there remained the problem that it was not possible to draw out the output line for the above-mentioned memory read information.

Purpose of the invention The purpose of the present invention is to solve the problems of the prior art;
By providing error correction means that can commonly use the input information line and output information line, and means for holding input information other than check bits, it is possible to transfer input information at high speed. An object of the present invention is to provide an error correction circuit suitable for LSI implementation that can transfer error correction information when an error exists.

Features of the Invention According to the present invention, in an error correction circuit that corrects errors in a plurality of pieces of information when transferring these pieces of information in parallel, input information including check bits for error correction and output information after error correction are connected to a common input/output circuit. an error correction means for inputting and outputting information via a line; a means for inputting and holding information other than check bits among the input information added to the error correction means; There is obtained a transfer information error correction circuit characterized in that it is configured to include a selection means that receives the output, selects the information, and transfers the selected information to the request source.

Next, an error correction circuit according to the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of a first embodiment of the present invention. In the figure,
The error correction circuit includes information selection control circuits 1-1 to 1-
5, an error correction circuit 2 including data control circuits 2-1 and 2-2, and an information holding circuit 3 that receives and holds memory read information.
It is composed of: Furthermore, the memory module 4 is composed of memory blocks 4-1 and 4-2. Among the above, the error correction circuit 2 includes data control circuits 2-1 and 2-2, respectively.
It also includes an error check code generation circuit, error detection circuit, and error correction circuit.
Reading and writing can be performed via information lines that share input and output respectively. The read information holding circuit 3 is
It receives read information from the memory module 4 via the data system selection circuit 1 and holds it.

To explain the operation of the embodiment configured in this way, first, input information given to the shared input/output information line 101 is transmitted through the information selection control controlled by the control line 24 or 22 in the data system selection circuit 1. Data control circuit 2-1 of error correction circuit 2 selected by circuit 1-1 or 1-3;
or transferred to 2-2. This transferred input information is checked for errors in the error correction circuit 2, an error correction code is added, and then transferred to the memory module 4 via the information selection control circuit 1-2 of the data system selection circuit 1. Ru. This memory module 4 stores information with an error correction code added, which is transferred to the memory block 4-1 or 4-2 under write control from control lines 26, 28 and address lines 27, 29. .

Reading of information stored in the memory module 4 is similarly performed by signal control using control lines 26, 28 and address lines 27, 28. The read information passes through the data system selection circuit 1,
While being held in the direct read information holding circuit 3,
The information selection control circuit 1-1 or 1-3 is given to the information selection control circuit 1-1 or 1-3 under control by the respective control line 24 or 22.
to operate the data control circuit 2-1 or 2-
given to 2. First, the information held in the read information holding circuit 3 is selected by the information selection control circuit 1-5 under the control of the control line 25 and transferred to an external device (not shown) via the input/output information line 101. . Furthermore, the information read from the memory input to the data control circuit 2-1 or 2-2 is
After error checking and error correction, if there is an error, the existence of the error is reported to the above-mentioned external device via the error information line 102. Alternatively, if the error can be corrected, the data control circuit 2-
After correcting the error in 1 or 2-2,
The read error correction information is sent to the information selection control circuit 1-4, and under the control of the control line 21, the read error correction information is sent to the external device via the input/output information line 101.

In the above embodiment, two memory blocks are provided in the memory module, and two of the error correction circuits are provided.
We have shown an example in which two data control circuits are shared for input/output lines, reading, and writing.
It goes without saying that the numbers of memory blocks and data control circuits can be selected as desired. Further, the information read from the memory module passes through the data system selection circuit 1 and is transferred to the information holding circuit 3.
However, it can also be added to the information holding circuit after passing through a control circuit within the data system selection circuit.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. In this example, two memory blocks are used in the memory module 4 and two data control circuits are used in the error correction circuit 6. As in the first embodiment, the data control circuits 6-1 and 6-2 are each provided with common input/output lines, but the data control circuit 6-1 is used for reading out the memory module 4. The first point is that the data control circuit 6-2 is dedicated for writing.
There is a difference from the embodiment. Therefore, the data system selection circuit 5 includes an information selection control circuit 5-1 used for selecting read information, an information selection control circuit 5-2 used for selecting write information, and information held in the information holding circuit 3. An information selection control circuit 5-3 for sending readout information is provided. The overall operation including the information selection control circuit can be easily understood without further explanation.

Effects of the Invention As is clear from the above description, according to the present invention, the input/output information lines of the error correction circuit are shared, the number of signal lines is reduced, and the read information holding circuit is provided separately from the error correction circuit. By transmitting the read information via the memory card and later transmitting correction information if there is an error in the read information, the configuration is simplified, making it easier to apply to LSI, and increasing the transfer performance. It has a great effect on improving sexuality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional example of an error correction circuit applied to a storage device, FIG. 2 is a block diagram showing the configuration of a first embodiment according to the present invention, and FIG. FIG. 2 is a block diagram showing the configuration of a second embodiment. In the figure, 1 and 5 are data system selection circuits, 1-
1 to 1-5, 5-1 to 5-3 are information selection control circuits, 2 and 6 are error correction circuits, 2-1, 2-2, and 6.
-1, 6-2 are data control circuits, 3 is a read information holding circuit, 4 is a memory module, 4-1, 4-
2 is a memory block.

Claims (1)

[Claims] 1. In an error correction circuit that corrects errors in multiple pieces of information when transferring them in parallel, an error occurs when input information including check bits for error correction and output information after error correction are input/output via a common input/output line. a correction means, a means for inputting and holding information other than check bits among the input information added to the error correction means, and a means for receiving the output of the error correction means and the output of the holding means, and storing such information. 1. A transfer information error correction circuit comprising: selection means for selecting and transferring the selected information to a request source.