JPS63153655A - Memory access control system - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a memory area by providing a data switching means and an address switching means to use a memory area being used for a parity data area as the data area. CONSTITUTION:A data switching means 2 switching a data and a parity data and transferring them to a parity area 1 of a memory and an address switching means 3 switching a data address indicating the data storage location and the parity data address indicating the parity data storage location in case of switching and sending the result to the parity data area 1, are provided. In writing the image data and the picture data into the memory, the data switching means 2 switches the image data not written in the data area as the data to be stored in the data area 1 to be selected. The data is transferred to the parity data area 1, and written in the data address location switched by the address switching means 3.

Description

[Detailed Description of the Invention] [Summary] The present invention provides image data processing to improve memory usage efficiency when storing large amounts of image data, etc. that do not require parity data, in a storage device of an information processing device. [Industrial field of application] This device relates to a memory access control system, and is particularly used in information processing devices to store images, data, and images. The present invention relates to an access control method for a readable/writable memory that stores data, etc.

[Conventional technology]

Conventionally, there has been a memory access control system as shown in FIG.

In this method, when writing data transferred from the data bus to the address position specified via the address bus in the data area 10 on the readable/writable memory, the parity data creation unit 4 Create parity data for use in parity checking based on data. The parity data is written to the parity area 21 on the readable/writable memory at the address location for parity indicated by the address bus.

In parity checking, when code information in units of multiple bits, such as one character, is expressed in 8 bits, the data is expressed as a combination of 7 bits, and the remaining 1 bit is used as parity data (parity bit). In addition, the number of bits "1" included in the 8 bits is set to be odd or even, and the number is checked to see if it is odd (even). This makes it possible to determine whether the data input or output from the data area 1O is correct or incorrect. Therefore, in this example, the parity area requires 177 (approximately $14.3) of the data area capacity.

A parity check is performed in the parity check section 25, and if an abnormality is found in the parity meeting data, a parity error signal is output.

[Problem that the invention seeks to solve]

By the way, unlike code information in units of multiple bits, data such as image data and image data in which each bit information has its own meaning generally has a large amount of data, and requires a large capacity memory to store it. be done. Therefore, when memory capacity is limited, it is necessary to improve memory usage efficiency. Also, when processing image data, parity data is not normally used, but when storing image data using conventional memory access methods, parity data is typically not used.
Since the parity data area can only store parity data, the above-mentioned example had a problem in that approximately 14.3z of memory space in the data area was unused, resulting in low usage efficiency.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and is intended to provide a memory access method with high usage efficiency.

[Means for solving problems]

In order to solve this problem, the present invention, as shown in FIG.
and an address switching means 3 that switches between a data address that indicates the storage location of the data and a parity data address that indicates the storage location of the parity data and sends it to the parity data area 1 during switching.
It has been established that

[Effect]

As shown in FIG. 1, parity data is generally added when data corresponding to normal code information is stored in memory. In this case, the data switching means 2 selects parity data and transfers it to the parity data area 1. The parity Φ data is written to a predetermined position in the parity data area 1 designated by the address for parity ψ data switched by the address switching means 3 at that time, and is read out simultaneously when the data is read from the data area. and then subjected to parity check.

On the other hand, when writing image data to the memory, the data switching means 2 selects data such as image data that has not been written to the data area as the data to be stored in the parity data area 1. Switch.

The data is transferred to the parity data area 1 and written in the address position for data switched by the address switching means 3.

〔Example〕

Next, an embodiment of the present invention will be described based on FIG.

The data area 10 is for storing data transferred via the data bus at an address location designated by the address meeting bus. The parity data creation unit 4 stores data related to code information in units of multiple bits in the data area 1.
When storing the data as 0, parity data is created from the data.

The type of data in the address switching means 13 is normal data related to code information and the like.

The data address and the parity data address are switched based on a switching control signal that is output depending on whether the data is image data, image data, etc. that does not require parity data. The parity data area 11 stores parity number data for the code information switched by the data switching means 12, or image data, or data that cannot be stored in the data area 10 among the image data, and stores it in the address switching means 13.
The data can be stored at the address location switched by .

The parity check unit 15 performs a parity check based on the parity data read from the parity data area 11 and the data read from the data area 10 when there is a switching control signal for code information data. If there is an abnormality in parity, an error signal is output.If there is image data or a switching control signal to image data, an error signal is output without performing a parity check. I try not to.

This embodiment operates as follows.

The code information data transferred via the data bus is stored in the address position of the data area 10 selected by the address switching means 13. At this time, parity data regarding the data is created in the parity data creation section 4, and a control signal for switching to code information data is sent to the address switching means 13, data clipping means 12, and parity check section 15. Sent out. Then, the data switching means 12 selects the parity fist data and transfers it to the parity data area 11, and the address switching means 13 selects the parity fist data and transfers it to the parity data area 11.
The parity data address in the parity data area 11 that is the same as the address of the data to be stored in 0 is selected, and the parity data is written to the corresponding address position.

In this way, the parity data stored in the parity data area 11 is read out when data is read out from the data area 1O, and sent to the parity check unit 15 for parity checking, to determine if there is an abnormality in the parity. If the parity check unit 15
An error signal is output.

On the other hand, when writing the image data transferred via the data bus to the data area 10, a switching control signal for image data is sent to the address switching means 13, the data switching means 12, and the parity check section 15. is issued. Then, the data switching means 12 selects the image data or data that is not stored in the data area 10 and transfers it to the parity data area 11, and the address switching means 13 selects the data that is not stored in the data area 10 from among the image data and image data and transfers it to the parity data area 11. A data address different from the address of the data is specified, and the data is written to the address position of the parity data area 11 specified by the address switching means 13.

When data stored in the parity data area 11 is read out, it is not sent to the parity check unit 15, which has been disabled by the image data switching control signal, but is sent to the data bus.

〔Effect of the invention〕

Thus, according to the present invention, when storing a large amount of data that does not require parity data, such as image data or image data, in memory, the memory area used as the parity data area can be used as the data area. Therefore, it is possible to improve the efficiency of memory area usage.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. l, 11.21... Parity data area 2.12.
... Data switching means 3.13 ... Address switching means 4 ... Parity data creation section 10 ... Data area 15.25 ... Parity 0 check section B month's principle diagram 2 Figure 1

Claims (1)

[Claims] Data switching means (2) for switching between data and parity data and transferring the data to a parity data area (1) of a memory; A memory access control system comprising an address switching means (3) for switching an address and a parity data address indicating a storage location of the parity data and transmitting the same to a parity data area (1).