JPS63206855A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To simplify a program for data transfer, by constituting a system in such a way that a data memory is provided at every processor, and the same data is written on both data memories, and the data is read out at every processor. CONSTITUTION:When the data is transferred from a slave processor 2 to a master processor 1, an address bus 5 is connected to data memories 3A and 3B by address switching circuits 6A and 6B, and a data bus 8 to the data memories by data switching circuits 9A and 9B, respectively. In such a way, the processor 2 designates an address by the bus 5, and outputs and writes a write data to the bus 8. After writing being completed, reading are performed by connecting an address bus 4 to the memory 3B by the circuit 6B and a data bus 7 to the memory by the circuit 9B. Thus, it is possible to perform the data transfer, and also to perform the data transfer from the processor 1 to the processor 2 similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device for exchanging data between processing devices.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional data transfer device disclosed in, for example, Japanese Unexamined Patent Publication No. 58-14234. In the figure, (1) and (2) are main processing units that control and process according to a program. and a slave processing device, (3) is a data memo IJ that temporarily stores input data from the main processor [11 and the slave processor (2), +41 is a main memory device]
111 is an address bus for accessing the data memory (3), and (6) is the address bus for the slave processing device (2) to access the data memory 1.
Address bus (6) is an address switching circuit that connects either address bus (4) or address bus (6) to data memo January 31, ())
(8) is the data bus through which the main processing unit +1+ exchanges data with the data memory (3), (8) is the data bus through which the slave processing unit (21 exchanges data with the data memory (3), and (9) is the data memory This is a data switching circuit that connects either the data bus () or the data bus (8) to (3).

Next, the operation will be explained using an example of data transfer from the slave processing device it 121 to the main processing device (1). In order to store data from the slave processing unit 1 (21 to the data memory (3), the address switching circuit (6) connects the address bus (5) and the data switching circuit (9) connects the data bus (8) to the data memory. (3).As a result, the slave processor (2) specifies the address of the data memory (3) via the address bus (5), and connects to the data bus (
8), outputs the stored data to the specified address of the data memory (3), and increments the specified address by one. In this way, when all the data is stored in the data memo January 31, the number of stored data (the number of data inputs) is stored in the predetermined address of the data memory (3), and the address switching circuit (61) (4) and the data bus (7) is connected to the data memory (3) by the data switching circuit M (91).In response, the main processing unit +11 connects the data in the predetermined address of the data memory (3). The number of inputs is address bus (4) and data bus +71.
Transfer data is read from the data memory (3) via the data bus (7) while changing the designated address using the address bus (4) based on the number of input data. The same applies to data transfer from the main processing unit it+11 to the slave processing unit (2).

[Problem that the invention seeks to solve]

Since the conventional data transfer device is configured as described above, the data memory (3) is switched from the slave processing device (2) to the main processing device (1) by the address switching circuit (6). When the slave processing device (2) attempts to use the transferred data, the same contents as the data memory (3) must be stored in the slave processing device (2), and the main memory of the slave processing device (2) must be stored. As the address space decreases, the address space also decreases, and the data memory (3) during data transfer also decreases.
and the same content must be written to main memory,
There were problems such as the program became sloppy and the processing time was naturally long.

This invention was made to solve the above-mentioned problems, and it is possible to effectively use the address space without using the main memory of the main processing unit and the slave processing unit, and to simplify the program when transferring data. The purpose is to obtain a data transfer device called VC.

[Means for solving problems]

The data transfer device according to the present invention is provided with a data memory for each processing device, stores the same data in both data memories when transferring data from the processing device, and after the data transfer is completed, data memory is provided for each processing device. It is designed to output data.

[Effect]

The data transfer device according to the second aspect of the present invention provides a data memory for each processing device, and by transferring data between the processing devices, exclusively uses the address space of the data memory as the address space of the processing device, and Writing of transfer data also requires only writing it into the data memory, so the processing program is written in a quantity rate.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same reference numerals as in the conventional device indicate the same or corresponding parts, and (3A) is the main processing unit f (11 and the slave processing unit g).
lt (Data memory A, (3B) that temporarily stores input data from 2+ is also data memory B, (6A) and (6B), respectively. Data memory IJ A (3A)
, data memo! J B (3B) IC, an address switching circuit that connects either address bus (4) or address bus (5), (9A) and (9B) each data memory A (3A).

This is a data switching circuit that connects either the data bus (7) or the data bus (8) to the data memo IJB (3B).

Next, regarding the operation, from the slave processing device (2) to the main processing device t.
(Data transfer to 11 will be explained as an example. In order to store data from slave processing device it+21 to data memo IJ A (3A) and data memo IJ B (3B), address switching time i% (6A) and (6B) connects the address bus (5), and data switching circuits (9A) and (9B) connect the data bus (8) to data memo IJ A (3A) and data memo IJ B (:jB), respectively.
). As a result, the slave processor (2) specifies the addresses of data memory A (3A) and data memory B (3B) via the address bus (5), outputs write data to the data bus (8), and outputs the write data to the data memory. A
(3A) and the specified address of data memory B (3B), and increments the specified address by one. In this way, all data are stored in data memory A (3A
) and data memory B (3B), the number of written data (number of data inputs) is written to data memory A (3A).
and write to a predetermined address of data memory B (3B), and write to the address bus (4) by the address switching circuit (6B).
The data bus (7) is connected to the data memo IJB (3B) by the data switching circuit (9B). In response to this, the main processing unit (1) stores the data memory B (3
The number of data inputs within the predetermined address of B) is connected to the address bus (
4) and the data bus (7), and based on the number of inputs, data is read from the data memory IJB (3B) to the address bus (
4), the transfer data is read via the data bus (7) while changing the specified address. At that time, since the slave processing device (2) and the data memo IJ A (3A) remain connected, the slave processing device (2) can also read the transferred data in the same manner.

Further, data transfer from the main processing device (1) to the slave processing device (2) can be performed in the same manner.

3. In the above embodiment, when the main processor il+ is accessing data memory B (3B), the slave processor (2) cannot transfer the transferred data to the data memo 3). According to another embodiment shown below, even when the main processor (1) is accessing the data memo IJB (3B), the slave processor (2) writes the transferred data to the data memo IJB (3B). can be included.

An embodiment of a pond according to the present invention will be described below with reference to FIG. In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and data memo IJ A (3A) and data memo IJ B (3B) are respectively connected to data memory AA.
(3AA) and data memory AB (3AB) and data memory BA (3BA) and data memory BB (38B)
) with dual configuration, address switching port @ (6AA)
(6AB) (6BA) (68B) and data switching circuit (
9AA) (9AB) (9BA) (98B) also have a double configuration.

In this FIG. 2, for example, data memo IJ AA (3
When inputting data from the slave processor (2) to the data memory BA (AA) and data memory BA (3BA), the main processor (1
) reads data from data memo IJBB (38B).

Then, data memory AA (3A
A) and writing to data memo IJ BA (3BA) and data memo IJ BB (38
When reading from B) is completed, the address switching circuit (6
AA) (6AB) (6BA) (68B) and data switching circuit (9AA) (9AB) (9BA) (9
8B), the slave processing device (2) controls the data memory A
B (3AB) and data memory BB (38B), the main processing unit il+ writes data memory IJ BA
(3BA) ◇ [Effects of the Invention] As described above, according to the present invention, a data memory is provided for each processing device, the same data is written to both data memories, and the same data is written to each processing device. Since the configuration is configured to read data, the address space of the processing device can be used effectively, programming at the time of data transfer is simplified, and an inexpensive device can be obtained.

[Brief explanation of the drawing]

FIG. 81 is a block diagram showing a data transfer device according to an embodiment of the invention, FIG. 2 is a block diagram of a data transfer device showing another embodiment of the invention, and FIG. 3 is a block diagram showing a conventional data transfer device. 0 +11 [21 is the processing device, (31 (3A) (3B) (
3AAX3AB) (3BA) (38B) is data memory, +4H5) Fi address bus, (61 (6A) (6
B) (6AA) (6AB) (6BA) (68B) is the address switching circuit, (7+ +8+ is the data bus, [9
1 (9A) (9B) (9AA) (9AB) (9BA) (
98B) is a data switching circuit. In addition, in the figures, the same symbols indicate the same or corresponding parts.

Claims (2)

[Claims] (1) In a data transfer device that sends and receives data between processing devices, there is a data memory provided for each of the processing devices that temporarily stores the transferred data, and a data memory that temporarily stores the data transferred from one of the processing devices. 1. A data transfer device comprising switching control means for writing data into both data memories, respectively, and reading and outputting the stored data to the processing device after the writing is completed. (2) Two data memories are provided for each processing device, so that even when one processing device is reading data from one data memory, the other processing device can write data to the other data memory. A data transfer device according to claim 1, characterized in that the data transfer device is configured as follows.