JPS5818761A - Storage controlling system - Google Patents

Abstract

PURPOSE:To make an arrangement that operations can be performed with respect to optional bit positions in a storage area through one piece of memory operation request, by giving a simple operational function to a storing device. CONSTITUTION:When an operation request is made from the outside, an address and operation data to be transferred are simultaneously set in an address register 12 and an operation data register 15, respectively. When data is sent, a storing device 11 simultaneously starts a readout operation and the data thus obtained are held in a data register 13. The readout data are sent to the device which performs the request through the data register 13 and, at the same time, sent to an arithmetic circuit 14 through a readout data line 18. The arithmetic circuit 14 performs the operation of the above-mentioned inputted value (through line 18) and a value already preset in the operation data register 15, and sends the result to the storing device 11 through a writing data line 19. The storing device 11 executes a writing operation after the above-mentioned readout operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control method. A multiprocessing system is a data processing system that has two or more independently operating arithmetic and control units (processors) and can execute two or more programs simultaneously.

In the E-book multiprocessing system, a method is usually used in which a specific common area is prepared in a storage device or the like, and specific data is written into the area and read checking is performed to synchronize the processors. That is, to indicate that information in a specific area has been successively read out from the storage device.

Writing specific data indicates that one processor has performed a memory operation. However, in general read/write operations, if an access conflict for a specific area occurs, and one processor reads data and another processor reads the data before rewriting it, the problem between the processors may occur. The drawback was that synchronization could not be achieved properly.

To prevent this, conventionally, storage devices have been provided with a function called a memory lock. That is, by locking the storage device while a storage area is being manipulated at a specific address, access from the other processor is prohibited. Ai Fi.

A special operation request was prepared, and at the same time a specified area was read along with a specific area, a certain amount of data (all vAo'' or all 11#) was written to that area. .

By the way, in a computer system that performs paging (transfer processing performed page by page between an external page storage device and a real storage device), a table for address conversion is referred to, and some flag bits, etc. are changed. When attempting to do so, one processor reads the data, and until it rewrites the data after changing it, the memory lock mechanism is used as described above.
The other processor was controlling the table so that it would not read it.

However, according to the system that employs the above-mentioned locking mechanism, the memory lock extends over a wide range of areas, resulting in a decrease in efficiency as the locking operation extends to unnecessary areas, and furthermore, it takes two memos to rewrite the memory contents. There were efficiency drawbacks such as the need for recycling. Furthermore, according to the method of providing an area attached to a specific area, the efficiency is even worse than the above-mentioned memory lock method, and the memory usage efficiency is also deteriorated.

The present invention has been made based on the above-mentioned circumstances, and an object of the present invention is to provide a storage control method that realizes an effective multiprocessing system by providing a storage device with simple arithmetic performance.

The present invention will be described in detail below using one drawing. FIG. 1 is a block diagram showing an embodiment of the periphery of a storage device that implements the present invention. In the figure, 11 is a storage device in which programs and data are stored. The address to access (read/write) the memory device 11 is held in the address register I2 via the address data line 16. Data obtained from the storage device 11 is held in a data register 13.

Reference numeral 14 denotes an arithmetic circuit, to which the output of the data register 3 and the output of an arithmetic data register 15 to be described later are supplied, and the result of the arithmetic operation here is supplied to the storage device 11 via a write data line 19. Calculation data is set in the calculation data register 15 from the outside (central processing unit) via the calculation data line 17.

FIG. 2 is a data display example conceptually showing the operation of the present invention. In FIG. 1, (al is calculation data (line J 7
), (bl is the read data (line 1 B)
, (cl is the data written to the storage device 11 (
The contents of each line 19) are shown.

Hereinafter, the operation of the embodiment of the present invention shown in FIG. 1 will be explained in detail with reference to FIG. First, when an operation request is received from the outside, the address and operation data that are transferred are transferred through the address data line 16 and the operation data line 17, respectively, to the address register 12. It is set in the calculation data register 15.

The storage device 11 starts a read operation at the same time as the data is sent, and stores the obtained data in the data register I.
Hold at 3. The read data is sent to the requesting device via the data register 13, and is also sent to the arithmetic circuit 14 via the read data line 18.

The operation (b) path 14 performs an operation between the input value (line 18) and a value already set in the operation data register 15 (
(eg, logical sum, logical product, etc.) and supplies the result to the storage device 11 via the write data line 19. Following the read operation described above, the storage device 11 performs a write operation.

A concrete example of the above operation is shown in FIG.

That is, data '10000000' such as (al) is supplied to one input terminal of the arithmetic circuit 14 via the arithmetic data line 11, and the data '10000000' such as (al) is supplied to one input terminal of the arithmetic circuit 14 through the memory device 11.
(data such as bl "01010101'
Suppose that is supplied. Now, if the operation mode of the arithmetic circuit 14 is a logical sum, the logical sum operation of the above two inputs is performed in the arithmetic circuit 14, and (data such as C1 '1101
0101' is obtained. The nine contents obtained here are written to the memory device II via the write data line 19.

The data indicated by lbl is transferred to an external device such as a processor that has made a request, and the rewriting operation is realized by one memory operation request.

As explained above, the present invention provides a storage device with a simple arithmetic function so that an arbitrary bit position in a storage area can be operated with one memory operation request. It is possible to store different data or perform operations while reading data with a single memory operation request. Therefore, a mobile-like multiprocessing system can be realized.
Furthermore, even during paging operations, table operations are simplified and an effective multi-processing system can be constructed.

Although the above explanation has been made only regarding synchronization between processors, it is also applicable to synchronization between a processor and an input/output control device or between input/output control devices. Nowadays, as the trend toward distributed processing progresses and input/output control devices with functions comparable to processors exist, the present invention has great advantages. Abandoned.

Of course, the present invention can also be applied to communication control devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an actual example of the periphery of a storage device that implements the present invention, and FIG. 2 is a data display example conceptually showing the operation of the present invention. 11...Storage device, 12... Address register. 13... Data register, 14... Arithmetic circuit, 15
...Performance Nf-tare register. Applicant's representative Patent attorney Suzue Takehiko Figure 1 Ichiryoichi◆ Figure 2 I Ninini Ni ■I (b) E [coff ) 15 1゛8 ■Erotic ■Seal

Claims (1)

[Claims] In a storage device that receives an area designation, calculation data, and operation request transferred from the outside, continues writing according to the received operation request, and reads data in the specified area and transfers it to the device that made the request. 1. A storage control method characterized in that, in addition to transferring, arithmetic operations are performed between received arithmetic data and read data, and a rewriting operation is performed with one memory operation request.