JPH0236011B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding access to a storage key provided for storage protection and management of a main storage device in a computer system, access to a storage key that is divided into a plurality of partial keys for different control purposes is provided. Aiming at a storage key access control scheme that improves efficiency, the invention comprises a plurality of different memory devices and a storage key controller, each storage key consisting of a plurality of different types of partial keys, and each memory device comprising: The corresponding partial key of the required storage key is held corresponding to each different partial key type, and when a request from the storage key control unit is received, the partial key to be held for the storage key specified in the request is stored. When the storage key control unit receives a predetermined storage key read request from the requesting device, the storage key control unit requests the memory device that holds the partial key specified by the read request to read the partial key. The partial key is read out, a predetermined signal that differs depending on the type of the partial key is attached to the read partial key, and the read partial key is transferred to the requesting device.

[Industrial application field]

The present invention relates to an access control method for a storage key provided for storage protection and management of a main storage device in a computer system.

The memory key is provided as a means of controlling access to the main memory for so-called memory protection of the main memory. Each storage key consists of a 1-bit access code and 1-bit read protection bit.

Furthermore, in a known virtual storage system, one reference bit and one change bit are allocated and held for each storage area divided into pages as data for controlling page replacement in the main storage device. In some cases, it is well known that the access code and the protection bit are combined and managed as a set of storage keys.

[Conventional technology]

As mentioned above, the storage key is the access code and read protection bit part (hereinafter referred to as ACC/
If the direct control purpose is different, such as the reference and change bit part (hereinafter referred to as the F part) and the reference and change bit part (hereinafter referred to as the R/C part), and the frequency of access and speed requirements are different, the processing efficiency In some cases, both are stored in different memory devices in consideration of economic efficiency.

FIG. 2 is a block diagram showing an example of the configuration of such a computer system. In the figure, a requesting device 16 such as a central processing unit (hereinafter referred to as CPU) is a main memory access control device (hereinafter referred to as CPU).
Data stored in the main storage device (hereinafter referred to as MSU) 11 can be accessed through the MCU (hereinafter referred to as MSU) 12 .

When providing a storage key as described above for the storage area of such data, when the R/C unit accesses the data area, rewriting processing is always automatically performed in parallel with the access, and the processing Since speed affects the speed of access to the data area,
The R/C section needs to be stored in a relatively high-speed memory, and for example, a high-speed storage key memory 13 is provided in the MCU 12 for storage. On the other hand, as for the ACC/F section, there is no requirement for high-speed access as compared to the R/C section, so for example, separate from the normal data storage area in the MSU 11, a storage key area 14 is carved out and the ACC/F section is stored. Remember.

The request source device 16, for example, the CPU, has special instructions required for each of the ACC/F section and the R/C section, for example, in order to access the storage key, and when these instructions are executed, the request source device 16 device 16
sends the address of the main storage area corresponding to the storage key and whether it is an ACC/F section or an R/C section (hereinafter referred to as partial key type) to the MCU 12 to request access.

For example, if the request is a read request,
The storage key control unit 15 of the MCU 12 is the request source device 1
When request 6 is received, depending on the partial key type,
If it is an R/C unit, it accesses its own storage key memory 14, reads out the partial key determined by the designated storage area address, and transfers it to the requesting device 16. If it is an ACC/F unit, it issues a storage key access request to the MSU 11 and relays the partial key read and transferred by the MSU 11 to the requesting device 16.

Here, if the request source device 16 is, for example, a CPU that performs so-called pipeline parallel processing, a read request for the ACC/F part of the access request is issued to the MCU 12, and the read is performed. It may happen that the next R/C unit read request is issued earlier.

In such a case, if a high-speed memory is used for the R/C unit as described above, the requesting device 16 may receive the later requested partial key of the R/C unit first, or may receive both at the same time. There is a possibility,
In this case, if the request source device 16 processes the read results as being able to receive them in the order of requests, an inconvenient processing result may occur.

Therefore, to prevent this situation from occurring,
For example, the storage key control unit 15 of the MCU 12 stores the order of access requests, transfers the read result of the previous request to the requesting device 16, and then controls the read result of the next request to be transferred. , to enable the requesting device 10 to perform normal processing.

[Problem to be solved by the invention]

In order to carry out the processing in consideration of the order of requests as described above, the control of the storage key control unit 15 becomes complicated, and in order to maintain the order, the transfer of information read earlier is forcibly delayed. From the perspective of the requesting device 16, there was a problem in that the access time was unnecessarily extended.

The present invention aims at a storage key access control method that solves the above problems and improves the efficiency of access to a storage key that is divided into a plurality of different partial keys for different control purposes.

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of a storage key access control system, which includes a plurality of different memory devices 22 and 23 and a storage key control unit 20, and each storage key is made up of partial keys of a plurality of different partial key types. , each memory device 22, 23 corresponds to a different partial key type, holds the corresponding partial key of the required storage key, and upon receiving a request from the storage key control unit 20, stores the corresponding partial key. When the storage key control unit 20 receives a predetermined storage key read request from the request source device 21, the storage key control unit 20 reads out the partial key held for the storage key specified by the storage key specified by the read request. Memory device 2 that holds
2, 23 and reads out the partial keys, attaches predetermined signals 3, 4 that differ depending on the type of the partial keys to the read partial keys 1, 2, and transfers them to the requesting device 21. .

[Effect]

With this control method, when a storage key is read from a memory device and transferred to an access request source, the transfer information indicates which part of the storage key it is.
Add a signal to display the partial key type.

This allows the requestor to receive and process each partial key at the required location, or to receive both parts at the same time.

Furthermore, the control of the storage key control unit for this purpose can be carried out simply by adding one bit of a signal indicating the partial key type to each partial key transfer line of the storage key.
This can be achieved relatively easily.

〔Example〕

Similarly to the above example, the memory device 22 in FIG. 1 is a main memory device similar to the conventional case, and the memory device 22 in FIG. A part of the area is used as a storage key area to store the ACC/F parts of all storage keys. Similarly, the memory device 23 is comprised of a storage key memory consisting of a high speed memory provided in the MCU.

When the control unit 24 of the storage key control unit 20 receives a storage key read request from the request source device 21 such as a CPU, the control unit 24 reads the storage key from the memory device 22 or 23 based on the main storage address and partial key type specification of the request.
Read the designated partial key of the memory key from , and store the read information in ACC/F register 1 or R/C.
set in register 2.

Further, at the same time as setting the read information to register 1 or 2, latch 3 is set on for reading from the ACC/F section, and latch 4 is set on for reading from the R/C section.

The outputs of the latches 3 and 4 are sent to the requesting device 21 via signal lines 5 and 6, respectively, and become a signal indicating the type of partial key.
and 8, and sends the contents of the ACC/F section register 1 and the R/C section register 2 to the requesting device 21.

When the control unit 24 turns on the latch 9 for a required time at an appropriate timing and sends an output valid signal to the signal line 10, the request source device 21 turns on the signal lines 5 and 6 while the signal line 10 is on. The outputs of the gate circuits 7 and 8 corresponding to the signal line that is turned on are received as partial key information of the read result.

FIG. 3 is a diagram illustrating an example of the timing of reading a memory key. Conventionally, as shown in FIG. 3a,
Even if a read request 31 is issued, the processing of the next request 31 is delayed until the previous request (ACC/F section read request 30 in the example shown in the figure) is completed, and the read request due to the previous request is completed as shown in the figure. After the result 32 is transferred by the output valid signal 33, the next request is processed, and only at the timing indicated by the read result 34 and the output valid signal 35 can the processing of the subsequent request be completed.

However, in the case of the present invention, since a signal indicating the partial key type is added, it is possible to process both requests in parallel, and as shown in b, the ACC/F section and the R/C section read out at the same time. Even if there is a timing relationship, processing can be performed normally without delay.

In addition, in the above explanation, an example was explained in which the memory key is divided into two types of partial keys, but it is clear that even if there are three or more types of partial keys, the same control can be performed using the configuration similar to the above. be.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in controlling access to a storage key in a computer system, a request source can use a relatively simple configuration to control partial keys for different control purposes. Information can be received where it is needed, and both parts can be received at the same time, reducing the cost of storage key access control.
It has a remarkable industrial effect of increasing speed and speed.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of the present invention, Figure 2 is a block diagram showing the configuration of the present invention.
The figure is a block diagram of a configuration example of a computer system, and FIG. 3 is an explanatory diagram of storage key read timing. In the figure, 1 is an ACC/F section register, 2 is an R/C section register, 3, 4, and 9 are latches, and 7, 8
1 is a gate circuit, 5, 6, and 10 are signal lines, 11 is a main memory device, 12 is a main memory access control device, and 13
is a storage key memory, 14 is a storage key area, 15,
20 is a storage key control unit, 16 and 21 are request source devices, 22 and 23 are memory devices, and 24 is a control unit.

Claims (1)

[Claims] 1. It has a plurality of different memory devices 22, 23 and a storage key control unit 20, each storage key is composed of a plurality of partial keys of different partial key types, and each memory device 22, 23 corresponds to the different partial key types and holds the corresponding partial keys of the required storage key, and the storage key control unit 2
0 request, the storage key controller 20 reads the partial key held for the storage key specified in the request, and when the storage key control unit 20 receives a predetermined storage key read request from the requesting device 21, , requests the memory devices 22 and 23 that hold the partial key specified by the read request to read out the partial key, and sets the read partial keys 1 and 2 to the partial key corresponding to the type of the partial key. Different predetermined signals 3, 4
1. A storage key access control method, characterized in that the storage key access control method is configured to forward the request source device to the requesting device.