JPH0570867B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for responding to access requests from each element processor in a multiprocessor system.
The present invention relates to a parallel processing control device that provides storage location information of data to be processed.

(Prior Art) Multiprocessor systems have two methods: increasing the number of requests processed by the system per unit time by assigning a separate processor to each request, and processing each request jointly using multiple processors. There are methods to shorten the processing time of individual requests by processing, and these methods are used depending on the field.

Among these methods, methods in which individual requests are jointly processed by multiple processors include shared memory that can be connected to multiple processors, and multiport page memory (Mamoru Tanaka, Multiport Page-Memory).
Archteeture and A Multiport Disk−Cache
System, New Generation Computing 2,
1984), a system is used in which each processor specifies a data storage location, and the data stored at that location is referenced and data is written to that location.

In this kind of parallel processing, when each processor accesses the storage device, it is necessary to arbitrate which data each processor should handle, and this processing is an important step in improving system performance. It's becoming a netsuku. For example, as shown in FIG. 5, a pair of employee number and employee name is stored as data in the storage device 1, and a message such as "Find the name of the employee whose employee number is 149828 from among them" is stored in the storage device 1. requests to multiple processors P ₁ , P ₂ ,
Consider the case of joint processing using ..., Pn. however,
It is assumed that some of these data are stored in a page of a certain fixed size. In this case, each processor P1 to Pn reads a page storing a pair of employee number and employee name from the storage device, and checks whether the employee number is equal to the condition for each of the data contained therein. This is an inspection, but if a page is read multiple times by several processors, or if a page is not read by any processor,
I can't get the correct result. Therefore, it is necessary to ensure that all pages are read only once by some processor.

The following two methods are conventionally known as means for ensuring this.

The first method is to determine in advance which pages each processor is responsible for before starting processing. For example, if the number of processors is n, and each page is given a serial number starting from 0, the i-th (i = 0, 1, ..., n-1) processor has the remainder when the serial number is divided by n ( Process pages equal to i-1). This method has the advantage of requiring less communication between processors, since the processor in charge of each page is determined from the beginning. However, this method
If the number of processors cannot be changed during processing, and if the processing load differs depending on the data, processing time will vary depending on the processor, and the overall processing time will be the processing time of the processor that performed the heaviest load processing. There are disadvantages such as the fact that

On the other hand, the second method uses a shared memory that can be accessed by each processor, and stores therein information that should be commonly referenced among the processors. For example, the storage location of the next page to be read from the storage device is stored in the shared memory. Each processor then reads the data at that location from the storage device and updates the value of the storage location to the storage location of the next page to be read. In this method, each processor can process the next page in the order that it finishes processing one page. Therefore, it is possible to add or remove processors during processing, and it is also possible to reduce variations in processing time between processors, thereby shortening the overall processing time. However, in this method, the period between when a certain processor refers to a storage location on the shared memory and when it is updated, that is, between reading the storage location information and
During the period of writing for updating, it is necessary to prevent other processors from referencing or rewriting the information. This type of processing will be referred to as synchronous processing here.The disadvantage of synchronous processing using shared memory is that synchronous processing must be performed exclusively, so it cannot be used with multiple processors, such as multi-board page memory. Therefore, even if storage devices that can be accessed simultaneously are used, the latent data transfer ability of the storage devices cannot be utilized due to synchronous processing. In addition, as shown in Figure 6, the original page input/output time by the data processing device is T, and the time required for synchronization processing is xT.
In this case, since only one processor can operate in the synchronous processing part, there is a drawback that the longer the synchronous processing time is, the more the degree of parallelism cannot be increased even if the number of processors is increased.

(Problem to be Solved by the Invention) As described above, in parallel processing by multiprocessors using conventional shared memory, it is necessary to share the processing of data stored in a storage device with each processor. Synchronization processing has been an obstacle to improving performance.

An object of the present invention is to provide a parallel processing control device that can speed up such synchronization processing and contribute to improving the processing efficiency of a multiprocessor system.

[Structure of the Invention] (Means for Solving the Problem) The present invention is connected to a multiprocessor system including N element processors, and transmits data to be processed to the element processor to which an access request has been output. A parallel processing control device for providing storage location information, comprising a storage means for storing storage location information of the data to be processed to be outputted when an access request is received next time, and a storage means for receiving an access request from the element processor. , when i is an integer from 1 to N, a number output means for calculating the number of processors requesting access simultaneously from the first element processor to the i-th element processor for each i; an addition means for adding the number obtained by the number output means and storage position information stored in the storage means for each i; and a first element processor that adds the storage position information stored in the storage means; an addition result output means for outputting the addition result for (i-1) of the addition means to the i-th element processor; and updating means for updating storage location information of data to be processed.

(Operation) According to the present invention, when an access request from the element processor is received, the number of processors that are simultaneously requesting access is determined by the number output means, and this number is added to the data storage location. Since the storage location information of the data to be processed is updated, there is no need for the element processor that read the storage location information to rewrite the storage location information in the next write cycle, and the next can respond to access requests from other processors. Therefore, according to the present invention, the speed of synchronization processing is increased by the amount of time required to rewrite the storage position information, contributing to improvement in the processing efficiency of the multiprocessor system.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing the configuration of a parallel processing control device according to an embodiment of the present invention. This parallel processing control device 10 includes four element processors P ₁ , P ₂ , P ₃ ,
P ₄ and these four element processors P _1
〜P4 , input register 11 _1〜1
1 ₄ , control memory 12, and four adders 13 ₁ to
13 ₄ , storage section 14, and output registers 15 ₁ to 1
It is composed of 5 and ₄ .

That is, the access request signal output from each element processor _P1 to _P4 is "1" when an access is requested;
The other 1-bit signals that are "0" are input to the input registers 11 ₁ to 11 ₄ via the corresponding input ports 11 to 14, respectively. Each 1-bit output from input registers 11 ₁ -11 ₄ is provided as a 4-bit input to control memory 12 . The control memory 12 is a table having an input-to-output relationship as shown in FIG. That is, the output _M1 is a 1-bit output, which is "1" when the processor _P1 issues an access request;
At other times, it becomes "0". Output _M2 is a 2-bit output that indicates the number of processors issuing access requests among processors _P1 and _P2 . Output _M3 is a 2-bit output that is output by the processor.
It shows the number of processors issuing access requests among P ₁ , P ₂ , and P ₃ . Output _M4 is a 3-bit output indicating the number of processors issuing access requests among processors _P1 , _P2 , _P3 , and _P4 . Output M ₁ of these control memories 12 ~
M ₄ is given to one input of adders 13 ₁ to 13 ₄ . The adder ₁₃₄ serves as a means for updating the storage address of the next data to be processed, and its output is input to the storage section 14 to update the contents of the storage section 14. The storage unit 14 is a 16-bit register in which storage addresses of data to be processed are stored. The output of this storage section 14 is stored in an output register 15.
₁ and output port _O1 to the processor _P1 , and is also provided as the other input of four adders ₁₃₁ to ₁₃₄ . Adder 13 ₁ ,
The outputs from 13 ₂ , 13 ₃ are output to output registers 15 ₂ ,
15 ₃ and 15 ₄ , respectively, and further connected to the processors P 2 and ₁₅ through output ports O ₂ , O ₃ and O ₄ , respectively.
It is output to P ₃ and P ₄ .

That is, since the contents of the storage section 14 are output as they are to the output port _O1 , the processor _P1 always uses the storage section 14 regardless of whether the other processors _P2 to _P4 have issued an access request. The data at the address pointed to will be processed.

Furthermore, since the adder ₁₃₁ outputs the result of adding the contents of the storage unit 14 and the output _M1 of the control memory 12 to the output port _O2 , the processor
_P2 processes the data at the address +1 of the contents of the storage section 14 when the processor _P1 issues an access request at the same time, and otherwise processes the data at the address pointed to by the contents of the storage section 14.

Since the adder ₁₃₂ outputs the result of adding the contents of the storage unit ₁₄ and the output _M2 of the control memory 12 to the output port O3, the processor _P3
The data at the address obtained by adding the number of processors that are simultaneously outputting access requests among the processors P ₁ and P ₂ to the contents of the storage unit 14 is processed.

Furthermore, since the adder ₁₃₃ outputs the result of adding the contents of the storage unit 14 and the output _M3 of the control memory 12 to the output port _O4 , the processor
P ₄ processes data at an address obtained by adding the number of processors outputting access requests at the same time among the processors P ₁ , P ₂ and P ₃ to the contents of the storage unit 14 .

Then, in the storage unit 14, the output M ₄ of the control memory 12, that is, the number of processors outputting the access request among the processors P ₁ to P ₄ is added to the current storage content by the adder 13 ₄ . It is added and newly stored. As a result, the contents of the storage unit 14 are updated.

FIG. 3 shows an example of a processing flow when each processor reads all data stored in a storage device using this parallel processing control device. In this example, each processor knows the number of data to be processed, and determines the magnitude of this number of data and the contents (S1, S2) obtained from the output ports of the parallel processing control device (S3). ), it is determined whether there is still data to be processed, and if there is data to be processed, the data is read (S4) and processed (S5). As can be seen from this example, by using a parallel processing controller, each processor does not have to consider the operations of other processors, and can speed up overall storage access, including synchronization processing. can be converted into

FIG. 4 shows another embodiment of the invention.

This parallel processing control device 20 is connected to four element processors P ₁ to _{P 4} via a shared bus 30 .

The parallel processing control device 20 has a configuration in which an interface circuit 21, an address selection circuit 22, a storage section 23, and an adder 24 are connected via an internal bus 25.

The storage unit 23 that stores the storage location of data to be processed is composed of register files, and each register is assigned a different address on the shared bus 30. Therefore, when there are various sets of data to be processed in parallel, the storage location of the next data to be processed can be stored for each set of data.

An access request from an element processor is made by executing a read from a register in the register film that stores the storage location of the data to be processed, and the data storage location is read as the data read by executing the read. Given. That is, when a certain processor Pi issues a read request to a register in the register file, which is the storage section 23, the contents of that register are first read as follows.
The data is sent to the interface circuit 21 via the internal bus 25 of the parallel processing control device 20, and further sent via the shared bus 30 to the processor Pi that issued the read request. At the same time, the parallel processing control device 20
The contents of the register are sent to the adder 24 via the internal bus 25 of the adder 24, and the result of adding 1 to the adder 24 is
Control the data to be stored in the same register again.

In this embodiment, the adder 24 is a means for updating the storage address of the next data to be processed.
The synchronization process can be sped up by the addition operation by 4.

Further, in this embodiment, the parallel processing control device 30 and each element processor P ₁ to
_P4 , so two or more access requests will not arrive at the parallel processing control device at the same time due to the action of an arbitration unit (not shown). Therefore, by completing the above processing within the read cycle corresponding to the access request, data storage locations can be provided to access requests from a plurality of processors without conflict. Compared to the first embodiment, this embodiment has the disadvantage that the processors cannot issue access requests at the same time.
This is significantly advantageous in terms of the amount of hardware required for implementation. Furthermore, compared to synchronous processing using shared memory, exclusive control from element processors is not required, and the time required for synchronous processing can be shortened.

[Effects of the Invention] As described above, according to the present invention, as the element processor reads the storage location information of the data to be processed, the updating means reads the storage location information of the data to be processed. Since the storage location information is updated, there is no need for the time needed to rewrite the storage location information as in the past, and the synchronization process is speeded up accordingly. Therefore, it can contribute to improving the processing efficiency of the multiprocessor system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a parallel processing system using a parallel processing control device according to an embodiment of the present invention, FIG. 2 is a diagram showing the contents of a control memory in the same parallel processing control device, and FIG. A diagram showing a processing flow of a processor in a processing system, FIG. 4 is a block diagram of a parallel processing system using a parallel processing control device according to another embodiment of the present invention, and FIG. 5 explains an example of search processing in a database. FIG. 6 is a timing diagram of parallel processing including conventional synchronous processing. 1...Storage device, 10, 20...Parallel processing control device, 11 ₁ to 11 ₄ ...Input register, 12...
Control memory, 13 ₁ to 13 ₄ , 24...Adder, 1
4, 23...Storage section, ₁₅₁ to ₁₅₄ ...Output register, 21...Interface circuit, 22...
Address selection circuit, 25...internal bus, 30...
Shared bus, _P1 to _P4 ...element processors.

Claims (1)

[Scope of Claims] A parallel processing control device that is connected to a multiprocessor system including 1N element processors and provides storage location information of data to be processed to the element processors to which access requests have been output. a storage means for storing storage location information of the data to be processed to be outputted the next time an access request is received; and upon receiving an access request from the element processor, i is an integer from 1 to N; When,
a number output means for calculating for each i the number of processors requesting access at the same time from the first element processor to the i-th element processor; an adding means for adding storage position information stored in the storage means for each i; and outputting the storage position information stored in the storage means to a first element processor; The addition result for 1) is the i-th
The present invention is characterized by comprising: an addition result output means for outputting to the element processor; and an update means for updating storage position information of the data to be processed using the addition result for N of the addition means. Parallel processing control device.