JPS63103342A - Main memory controller - Google Patents

Abstract

PURPOSE:To improve the processing speed of a main memory controller by writing the address of the data fetched by partial storage and the address for the next partial storage after merging both data in each other when these two addresses are equal to each other. CONSTITUTION:The address, store data and byte mark received from a CPU 0 are fetched by a memory in a partial storage mode. Then the address and the store data are supplied to address pipes 7 and 29 respectively. If a storing request is issued to an address equal to the one which is presently fetched, the store address kept waiting at an address buffer 2 is compared with the address given from the pipe 7 by a comparator 11 or 12. When coincidence is obtained between both addresses, the data on a store buffer 22 or 24 is merged with the data given from the pipe 29 by a data merging circuit 35. Furthermore the store data to be supplied to the memory functions to merge the output of the circuit 35 and the fetch data on a register 34 by a store data merging circuit 26. This merge output is set to a register 28 with addition of a bit via an ECC generator 27.

Description

[Detailed Description of the Invention] [Overview] Writing multiple units (for example, 8 bytes) of data in one access (this is referred to as a store in this specification)
In a storage device configured to perform reading (also referred to as fetch in this specification),
When rewriting part of the data (for example, 4 bytes) (
In this specification, this is referred to as a partial store.
In order to generate an ECC bit, the data at the corresponding address is read, this data is merged with the data to be written, the ECC bit is added, and then the data is written, which requires a large amount of time to occupy the storage device. For this reason, there was a problem that the system's processing performance decreased when partial stores to the same bank were performed consecutively.In order to solve this conventional problem, the present invention addresses the fetched data for partial stores. and the address at which the next partial store should be performed, and if they are the same, both data are merged and written, thereby reducing the number of accesses to the storage device and improving processing performance. The configuration of the i@11O4 device is disclosed.

[Industrial Application Field] The present invention relates to the configuration of a main memory control device of an information processing device, and in particular, to efficiently perform actual access to the main memory when partial stores to the same address are successive. Possible circuit II! Related to the Hollow.

[Prior Art] FIG. 2 is a block diagram showing an example of the configuration of an information processing device, in which 51 is a CPU (0), 52 is a CPU (1), and 53 is a block diagram showing an example of the configuration of an information processing device.
54 represents a main memory controller (MCtJ), and 55 represents a memory (MEM).

The main memory control device 54 is a CPU (0) 51. CPU (1)
52, receives a request for storing data in the memory 55 from the CHP or fetching data from the memory 55, and plays the role of efficiently transferring the data to the memory according to the free space of the memory bank.

FIG. 3 is a block diagram showing an example of the configuration of a conventional main memory control device, in which 61 to 62 are address buffers of CPU0, 63 to 64 are address buffers of CPUI, 65 is an address selector, and 66 is a memory address register. ,6
7 is the address pipe, 68 is the CPUO address bus,
69 is the address bus of CPU1, 70 is the address bus to memory, 71-72 is the data buffer of CPU0, 7
3 to 74 are CPUI data buffers, 75 is a data selector, 76 is a data merging circuit, 77 is an ECC generation circuit, 78 is a store data register, 79 is a data pipe, 80 is a CPU0 store data bus, 81 is a CPU1
a store data bus; 82 is a memory fetch data bus;
83 represents a memory store data bus, and 84 represents a memory fetch data register.

When performing partial store from CPU0 in the main memory control device configured as shown in FIG.
When the store address and store data are sent via the data bus 80 and set in the address buffers 71 and 72,
Check the busy state of the memory bank corresponding to this address, and if it is not busy, the memory bank CPtJ 1, CHP ([l
After adjusting the priority relationship with il (not shown), the store address is set in the memory address register 66 via the selector 65. The store address is then sent to the memory via the memory bus 70. Further, this address is delayed by the address pipe 77 in accordance with the memory fetch timing and returned to the selector 75.

The store data has a priority like the address, but is not sent to the memory but sent to the data pipe 79 to match the memory fetch timing.

When the memory fetch is completed, the store data sent from the data pipe 79 is merged with the memory fetch data by the merging circuit 76 using the byte mark moving in synchronization with the data. This data passes through the ECC generation circuit 77, and store data to which an ECC bit is added is set in the data register 78 and sent to the memory via the memory store data bus 83, completing the partial store from the CPU0.

[Problems to be Solved by the Invention] As described above, when performing a partial store, a memory fetch is first performed, followed by a memory store.

Considering the case where partial stores are performed continuously, if the banks to which partial stores are to be stored are different, the partial stores are processed almost in parallel with a difference of one clock, as shown in Figure 4(a). However, if partial stores to the same bank are continuously requested (b
), first perform a memory fetch for the -th partial store, merge the fetched data with the store data from CPtJ and store it in the memory, and after this series of processing is completed, perform the next partial store. Enters a memory fetch cycle for.

That is, if partial stores to the same bank are performed consecutively, subsequent partial store processing will have to wait for a long time until the previous partial store processing is completed.

Continuous partial stores to the same bank often occur, for example, when the memory data width is 8 bytes or when software processes data in units of 4 bytes. Partial stores to the same address occur consecutively.

An object of the present invention is to provide a main memory control device that can improve processing speed by efficiently processing such partial stores to the same address.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by providing an address register that holds a memory address value related to a partial store for a certain period of time, and an address register that holds a memory address value related to a partial store for a certain period of time; a fetch data register that holds read data, a data register that holds data to be written to the address of the memory for a certain period of time, and an address buffer that holds a memory address value related to the next memory request;
a data buffer for holding data to be stored at the address in the memory; a means for comparing the contents of the address register with the contents of the address buffer; and a means for comparing the contents of the address register with the contents of the address buffer; The present invention is characterized by comprising means for merging the contents of the fetch data register, the contents of the data register, and the contents of the data buffer to generate data to be stored in the memory when the contents match the contents of the address buffer. This is accomplished by the main memory controller.

[Embodiment] FIG. 1 is a block diagram of one embodiment of the present invention, and shows 1 to 1.
2 is CPUO address buffer, 3-4 are CPU 1
address buffer, 5 is address selector, 6 is memory address register, 7 is address pipe, 8 is CPU
0 address bus, 9 is CPUI address bus, 10
is an address bus to the memory, 11 to 12 are address comparators, 13 to 14 are address match signals, 25 is a store data selector, 26 is a store data merge circuit, and 27 is an E
CC generator, 28 memory store data register, 29
is a store data pipe, 30 is a CPUO store data bus, 31 is a CPUI store data bus, 32 is a fetch data bus from memory, 33 is a store data bus to memory, 34 is a memory fetch data register, 3
5 represents a data merging circuit.

In Figure 1, address and store data from CPUO,
When a byte mark is sent and this is a partial store (if the byte mark is not all "1 pa"), first fetch it to memory, put the address and store data into address pipe 7 and data pipe 29, respectively, and then store from memory. Wait for data to be read. If a store request (partial store or full store) to the same address as the address currently being fetched is
If there is more data than puo, the memory bank is busy and the priority cannot be taken, so the user is forced to wait.

At the timing when fetch data is sent from memory, address comparator 1 compares the store address waiting in buffer 2 and the address sent from address pipe 7.
1 or 12 and if they match, the data in the data header buffer 22 or 24 from the data pipe 29 is merged in the merge circuit 35 according to the byte mark in the buffer. At the same time, as for the byte mark, the byte mark in the buffer and the byte mark from the pipe are ORed.

The data to be stored in the memory is stored in the merge circuit 2 according to the byte mark obtained by ORing the merge output of the data merge circuit 35 and the fetch data output from the register 34.
6, the ECC generator 27 adds an ECC bit to the output, sets it in the register 28, and stores it in the memory.

[Effects of the Invention] As explained above, according to the main memory control device of the present invention,
If a partial store to the same address in the memory of the same bank is requested again after a partial store, the processing related to these two partial stores can be completed within the time required for one partial store.
This has the advantage that memory can be used efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of an information processing device, FIG. 3 is a block diagram showing an example of the configuration of a conventional main memory control device, and FIG. FIG. 4 is a diagram explaining the partial store. 1.2.3.4 Address buffer, 5...
...Address selector, 6...Memory address register, 7...Address pipe, 8.9
...Address bus, 10...Address bus to memory, 11.12...Address comparator, 13.14...Address match signal, 21.
22.23.24...Data buffer, 25.
... Store data selector, 26 ... Store data merge circuit, 27 ... ECC generator, 28 ... Memory store data register, 29
... Data pipe, 30.31 ... Store data bus, 32 ... Fetch data bus from memory, 33 ... Store data bus to memory, 34...Memory fetch data register, 35...Data merging circuit agent Patent attorney Sada Igata - Half a block of blocks of one execution code of Mizuhato / Diagram

Claims (1)

[Claims] An address register that holds a memory address value related to a partial store for a certain period of time, a fetch data register that holds data read from the address in the memory, and a register that holds data to be written to the address in the memory for a certain period of time. an address buffer that holds the memory address value related to the next memory request; a data buffer that holds the data to be stored at the address in the memory; and a comparison between the contents of the address register and the contents of the address buffer. means for merging the contents of the fetch data register, the contents of the data register, and the contents of the data buffer when the next memory request is related to a partial store and the contents of the address register and the contents of the address buffer match; 1. A main memory control device comprising: means for generating data to be stored in a memory.