JPS6345652A - Invalidation processing system for information processor - Google Patents

Abstract

PURPOSE:To avoid the deterioration in performance due to the same invalidation processing and to improve the performance by using an invalid information degenerating circuit to perform the comparison of information and degenerating the undone invalidation processing among those subsequent invalidation processings under processes. CONSTITUTION:An invalidation information degenerating means 9 receives the invalidation information on registers 6a-6f of an invalidation information holding means 6 as well as valid bits 6h and 6g via invalidation information lines 16-a-16-h. It is confirmed that the coincidence is secured with invalidation addresses between a first vector store request and its following one as long as an AND is obtained through an AND gate 9-e. The information valid bit 6-h of a subsequent vector store request not subjected to invalidation processing yet is displayed invalid (=0) via an invalidation degeneration information line 17 based on said coincidence information. Thus it is possible to degenerate the invalidation processing to be carried out the invalidation information kept undone.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an invalidation processing method for an information processing device, and particularly to an invalidation processing method for valid data stored in a buffer storage means.

[Conventional technology]

Conventionally, in an information processing device having a vector processing device and a scalar processing device, invalidation processing of a buffer storage means is performed by rewriting data on the main storage device in response to a store request from the vector processing device, thereby rewriting a copy of the data. Since the contents of the data in the buffer storage means held in block units become invalid, this is done in order to guarantee the data in the buffer storage means against subsequent scalar load requests. In response to the vector store request, the vector store start address (B), the distance between vector store elements (D), and the number of vector store elements (
L) is retained as invalidation information.

A vector store area (B to B+LD) is created and held from B, D, and L, and an invalidation address generation circuit generates and holds the invalidation address (B, B+D, B+2D...B+LD).
) and execute invalidation processing for each, and in order to guarantee data for subsequent scalar loads until the processing is completed, in the case of access to the vector store area, the request is processed as a request to the main memory, and at this time, if a subsequent vector store request comes during invalidation processing, only invalidation processing for the subsequent vector store request can be performed.

This is held, and after the buffer storage means invalidation process associated with the first vector store request is completed, the subsequent invalidation process is executed again.

[Problem that the invention seeks to solve]

In the conventional invalidation processing method described above, the invalidation process of the buffer storage means associated with the first vector store request cannot be performed until the invalidation process of the buffer storage means associated with the first vector store request is completed. As a result, even if the invalidation process is exactly the same, it must be performed twice, and the same block that has already been invalidated will be invalidated again. However, the disadvantage is that the invalidation process takes time and the processing time of subsequent requests becomes longer.

[Means for solving problems]

The invalidation processing method of the information processing apparatus of the present invention includes a scalar processing means for processing a scalar request, a vector processing means for processing a vector request, and a scalar request and a vector request for the scalar processing means and the vector processing means. Request issuing means to be issued.

A main memory means for exchanging data with the scalar processing means and the vector processing means, and a copy of a part of the data in the main memory means, which is located between the main memory means and the scalar processing means. a buffer storage means for storing in block units and having a valid pit for displaying the block address and validity of the block; and a vector store that is sent together with the vector store request in response to the vector store request from the request issuing means. An invalidation processing means that creates an invalidation address for invalidation processing that invalidates the valid bits stored in the buffer storage means based on address information and performs the invalidation processing, and a request issuing means that sequentially issues the invalidation address. a revocation information holding means for holding a plurality of sets of revocation address information necessary for controlling the revocation processing means together with revocation request information in response to a vector store request; Compare the revocation information between each of the plurality of sets of revocation information, and if a match is detected, reset the matched revocation request information in the subsequent request in the revocation information holding means, and reduce the number of requests. It is configured to include invalidation information degeneration means for degenerating the invalidation information.

〔Example〕

Next, two aspects of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. An outline of its operation will be explained using FIG.

First, the invalidation process of the second normal buffer storage means 5 will be explained. When a store request is made from the vector processing means 2 to the main storage means 4 in a state where a copy of a part of the data in the main storage means 4 exists in the buffer storage means 5, the data is stored on the main storage means 4 via the vector request information line 11.

Control circuit 8 Hess door request is issued, main memory control information line 2
1, the instruction is executed. This means that the data in the main storage means 4 has been rewritten, and it becomes necessary to ensure the contents of the data in the buffer storage means 5.

Therefore, from the vector processing means 2, the vector store start address (B),
By holding the distance between vector store elements (D) and the number of vector store elements (L) in the invalidation information holding means 6, and sending the information to the invalidation processing means 7 via the invalidation processing information line 18. , from that information invalidate address (B, B+D, B+2D...B+L
D) is created, and the buffer storage means 5 is invalidated via the invalidation processing line 20.

Although the data stored in the buffer storage means 5 can be guaranteed by this, the data cannot be guaranteed for subsequent requests until the invalidation process is completed. Therefore,
A vector store area is created by sending the vector store information (B, D, L) held in the invalidation information holding means 6 to the control means 8 via the control information line 15, and the invalidation process is completed. By holding it until
A scalar load request for accessing the buffer storage means 5 sent from the scalar processing means 1 via the scalar request information line 10 is controlled so that it becomes a request for the main storage means 4 when it is within the vector store area.

Data is guaranteed by issuing a request to the main memory means 4 via the main memory control information line 21 and controlling the data to be returned from the main memory means 4 to the scalar processing means 1 via the data line 13.

This is the basic operation, but the present invention is characterized by the control method for the invalidation process by the subsequent vector store request sent during the invalidation process accompanying the vector store request. make use of.

explain. In order to simplify the explanation, invalidation information holding means 6
Let us take as an example a case where up to two pieces of vector store information can be held.

First, information associated with the first vector store request is held in the B register 6-a, D register 6-c, and L register 6-e, and the information valid bit 6-h is valid (=1
), if a vector store request comes as a subsequent request, B is sent via the vector store information line 12.
/Resosta 6-b.

Information is set in the D register 6-d and L' register 6-f, and the information valid pin 6-g is set to 1. It is assumed that the information valid bits 6-h and 6-g are reset when the invalidation process is completed.

At this time, the invalidation address associated with the subsequent vector store request is the same as the invalidation address associated with the first vector store request.
If it is the same as the response, there should be no need to perform invalidation processing associated with subsequent vector store requests. In other words, the fact that the invalidation addresses are the same means that the vector store start address, the distance between vector store elements, and the number of vector store elements are all the same.

(B=B', D=D', L=L') Therefore, the invalidation information degenerating means 9 is provided, and the invalidation information holding means 6
The invalidation information of the registers 6a to 6f and valid pins 6h and 6g is received via the invalidation information lines 16-a to 16-h, and the comparison circuit 9-a compares the value of the B register 6-a with the value of the B register 6-a. A comparison circuit 9-b compares the value of the D register 6-c and a value of the D register 6-d to detect a match, and a comparison circuit 9-c detects a match. The value of the register '6-s and the value of the L register 6-f are compared to detect a match, and each information valid pin is detected (6-h).

6-g information is ANDed by AND gate 9-d.

The respective output results are ANDed with 9-e, and if the AND is obtained from AND date 9-e, the invalidation address matches the first vector store request and the subsequent vector store request. Therefore, this -
Using the numerical information, the information valid pin (6-h) of the subsequent vector store request that has not yet been invalidated is displayed as invalid (=O) via the invalidation degeneration information line 17. When the invalidation process associated with the first vector store request is completed, the information valid bit 6-g is displayed as invalid from the invalidation processing means 7 via the invalidation completion information line 19.

The invalidation information holding circuit 6 is held when each information valid bit is valid, otherwise it is controlled to accept subsequent invalidation information, and when the holding circuit is full, subsequent instructions are inhibited. shall be carried out.

In this way, by comparing the information held in the invalidation information holding means 6 that has an information valid bit and displaying it as invalid if there is a match, it is possible to prevent invalidation that has not yet been performed. It becomes possible to degenerate the invalidation process that is likely to be performed based on the invalidation information.

〔Effect of the invention〕

As explained above, the present invention provides an invalidation information degeneration circuit, and by comparing information therein, it is possible to degenerate unexecuted invalidation processing among the subsequent invalidation processing during the invalidation processing, and the performance of the same invalidation processing is improved. This has the effect of avoiding a decline in performance and improving performance.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG. 2 is a configuration diagram showing an example of partial details thereof. Symbol explanation: 1... Scalar processing means, 2... Vector processing means. 3...Request issuing means, 4...Main storage means, 5...
Buffer storage means, 6... invalidation information holding means, 6-a.
...B register, 6-b...B register, 6-c...
・D register, 6-d...D Lunostar, 6-e...
L register. 6-f... L register, 6-g, 6-h... Information valid bit, 7... Invalidation processing means, 8... Control means, 9... Invalid information degenerating means, 9- a, 9-b, 9-c
...comparison circuit, 9-d, 9-e-AND
), 10--scalar request information line, 11--vector request information line. 12... Vector store information line, 13... Data line. 14...Data line, 15...Control information line, 16...
・Invalidation information line, 17... Invalidation degeneration information line, 18・
... Invalidation processing information line, 19... Invalidation end information line,
20... Invalidation processing line, 21... Main memory control information line. Figure 1 Figure 2

Claims (1)

[Claims] 1. A scalar processing means for processing a scalar request, a vector processing means for processing a vector request, a request issuing means for issuing a scalar request and a vector request to the scalar processing means and the vector processing means, and the scalar processing means and a main memory means for exchanging data with the vector processing means, and a main memory means located between the main memory means and the scalar processing means and storing a copy of a part of the data in the main memory means in units of blocks. buffer storage means having a valid bit for indicating the block address and validity of the block; and buffer storage means having a valid bit for indicating the block address and validity of the block; An invalidation processing means that creates an invalidation address for invalidation processing to invalidate valid bits stored in the storage means and performs the invalidation processing, and corresponds to vector store requests sequentially issued from the request issuing means. a revocation information holding means for holding a plurality of sets of revocation address information necessary for controlling the revocation processing means together with revocation request information; and a plurality of sets of revocation information stored and held in the revocation information holding means. Invalidation information degenerating means that compares the revocation information between each piece of revocation information and, when a match is detected, resets the matched revocation request information in the subsequent request in the revocation information holding means and degenerates the number of requests. An invalidation processing method for an information processing device, comprising: