JPH02294866A - Storage control system - Google Patents

Abstract

PURPOSE:To efficiently execute the coincidence control between an MS and a BS by a small number of FAAs by retrieving whether information in an area is inputted to the other processor or not, and executing the control so as to nullify the information concerned in the case it is inputted. CONSTITUTION:A storage area of a main storage device (MS) 1 is extracted, whether information in the area is inputted to buffer storage devices (BS) 31, 41 of the other processor or not is retrieved, and in the case it is inputted, the control is executed so as to nullify the information concerned. That is, this system is provided with a mechanism 250 for extracting an address for showing a stored area by detecting a common bit position and a value from addresses of plural store requests issued from processors VP0, VP1, a mechanism 251 for retrieving successively management tables 23, 24 of the BS in order to decide whether information of an extracted address area is inputted to the BSs 31, 41 in each scalar processor 3, 4 or not, and mechanisms 23 - 26 for nullifying it in the case it is inputted. In such a way, the coincidence security control can be executed normally by a small number of second management tables (FAA).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a storage control system, and more particularly to a coherence control system between a shared storage device and a buffer storage device in a multiprocessor system.

[Prior art]

In recent computer systems, main memory (MainSt.
The contents of the Suffer Storage (hereinafter abbreviated as MS) are stored in a buffer (or storage: L) storage device (hereinafter abbreviated as BS) composed of elements faster than the MS, and the contents are stored at high speed from the processing device. It allows for easy access.

Recently, so-called multiprocessor systems in which an MS is shared by multiple instruction processors each equipped with a BS have been attracting attention. When this occurs, control to ensure consistency between the MS and BS is required.

An example of such a technique described is Japanese Patent Publication No. 54-40182.

According to the method described in the above publication, a management table (Buffer^d) in which addresses in the MS are registered in the BS.
(hereinafter abbreviated as BAA)
In addition to providing a second management table (Front Address Array,
(hereinafter abbreviated as FAA). This FAA is
This is a management table for checking store addresses that is referenced by other instruction processors, and is used to quickly process consistency control between MS and BS.

Furthermore, in order to process scientific and technical calculations at high speed,
Vector Processor
(hereinafter abbreviated as VP) has come to be used. This vP is a vector register (hereinafter referred to as VR) that holds vector data.
and a plurality of arithmetic units that operate on the vector data. As a control method for such a VP, many adopt an element parallel processing method in which vector data of one vector instruction is divided into multiple groups of elements and operations are executed in parallel for each group. In this case, when accessing the MS from the VP, processing is performed by assigning the divided elements to a plurality of access request control devices (requesters) in parallel.

A scalar processing device (Sc
Alar Processor (hereinafter abbreviated as SP) is used as a method for reducing the amount of FAA hardware required to process store operations from vP to MS in a shared MS system. 6
There is one described in No. 3-3800.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, multiple VPs as described above
No consideration was given to a multiprocessor system consisting of a processor and a plurality of SPs.

In other words, for a store request issued by one VP, it is necessary to search for FAAs corresponding to the BSs of all SPs, and for this purpose, it is necessary to search for FAAs corresponding to the BSs of all SPs.
If AA is provided, FAA for (number of VPs) x (number of SPs) will be required, and the amount of hardware will increase extremely, making it virtually impossible to implement the system.

On the other hand, if the number of FAAs is reduced, there is a problem that a large amount of time is wasted waiting for FAA search, resulting in a significant drop in system performance.

An object of the present invention is to solve the above-mentioned problems, and to provide a plurality of VPs each having a plurality of store requestors and a plurality of Ss each having a BS.
To provide a storage control method capable of efficiently controlling consistency between MSs and BSs with a small number of FAAs in a multiprocessor system consisting of MSs shared by P and these VPs and SPs. There is a particular thing.

[Means to solve the problem]

The storage control system of the present invention comprises a main storage device and two or more processors that share the main storage device, and each processor has a buffer storage device that holds a copy of a part of the information in the main storage device. In a multiprocessor system, one processor extracts a storage area of the main memory that has been rewritten within a predetermined period, and determines whether the information in the area has been taken into the buffer storage of another processor. In addition to searching, if the information has been retrieved, control is performed to invalidate the corresponding information in this buffer storage area.

In other words, there is a mechanism for extracting an address indicating a stored area by detecting common bit positions and values from the addresses of multiple store requests issued by the processor, and a mechanism for extracting the address indicating the stored area, and information on the extracted address area within each SP. B
This system includes a mechanism for sequentially searching the management table of the BS to determine whether the information has been imported into S, and a mechanism for invalidating the information if it has been imported.

In addition, in order to process the search for the above address area at high speed,
A management table (FAA) is provided exclusively for searching.

Furthermore, searching for FAA using the address of an individual store request can be completed in a shorter time than searching for FAA using the extracted address, or more efficient invalidation processing can be performed (reducing excessive invalidation processing). In case it is determined that the store request is possible, a mechanism is provided for switching between the two search means and processing according to an instruction from the VP issuing the store request.

[Effect]

According to the above-described means, a plurality of store requests issued by a VP are reduced to at least one extraction address, and an FAA corresponding to each SP is searched. by this,
Since it can be determined whether a certain area on the MS has been imported into the BS of each SP, FAA
Search processing can be performed normally with a smaller number of FAA than in the case where FAA is provided.

In addition, if the number of a series of store requests issued by a vP is small and it is determined that an FAA search using address extraction will require a longer time than an FAA search using individual store requests, or if the number of a series of store requests issued by a VP is If the address of the store request is distributed over a wide area in the main memory and it is determined that the FAA search using the address extraction process will result in excessive BS invalidation processing, the FAA search using the individual store request control to switch to processing. This makes it possible to increase processing time in specific cases associated with FAA search by address extraction processing and to reduce excessive invalidation processing (improving system performance).

〔Example〕

First, an embodiment of the invention will be described with reference to FIG.

FIG. 2 is a block diagram showing the configuration of the main parts of a multiprocessor system of a vector processing device showing an embodiment of the present invention.

In the figure, 1 is an MS, and the MSI is shared by the number of SPs 3.4 (two in this case) and a plurality of VPs 5.6. 2 is a storage controller (S) that controls requests from SP3.4 and VP5.6 to MSI.
(abbreviated as C).

The SP3 includes a BS31 and a BAA30 for registering the address in the MSI of this BS31. Further, the VP5 has a pair of VRs 51A and 51B, and store requesters 50A and 50B corresponding to these VRs. The above VR5IA, 51B is the data on MSI (
vector data).
It has the same functions as the BS31 in SP3 described above.

However, each VR 51A, 51B is a register and is managed by software, and is characterized in that hardware such as a BS does not perform control to ensure consistency of information with the MS 1.

SP4 and VP6 also have the same configuration as SP3 and VP6 described above. That is, SP4 is BAA4
0, Equipped with BS41, VP6 is VR61A, VR61B
and store requesters 60A and 60B.
These functions are similar to those described in SP3 and VP5 above.

In this embodiment, the VPs 5 and 6 execute calculations in an element parallel manner. For example, in VP5, VR51A, 51
When a store command is issued to store the data of B in a certain area of the MSI, the data of VR51A, 51B is divided into two element by element, and the data of VR51A and 51B are divided into two parts, such as the first element is Questa 50A1 and the second element is Questa 50B. Divide and allocate to Tsuri questa. The requesters 50A and 50B each have M
A store request is issued to S1. The above processing is the same in VP6.

SC2 is FAA2 which is a copy of BAA30 and 40
3 and 24, and a search mechanism 25.2 6 (Reference
e tlnit (hereinafter abbreviated as REF25, 26). These REFs 25 and 26 contain respective V
Store requests 50A, 50B corresponding to P5, 6.
a mechanism for extracting a stored area address from multiple store addresses sent from 60A and 60B;
Based on the extracted address, it is provided with a mechanism that sequentially searches the FAA to determine whether or not the area has been taken into BS31.41, and a search-only FAA corresponding to each BAA.

First, the overall operation when one vector store instruction is issued from the VP5 will be explained.

When one vector store instruction is activated in the VP5, vector store data is divided and allocated to a plurality of store requesters 50A and 50B using an element parallel method. The store request addresses issued from the plurality of store requesters 50A and 50B are sent to the SC2 via the signal lines 5a and 5b, and are passed to the REF 25 to extract the common bits of the sequentially sent addresses. "area address extraction processing" is performed. The extraction address obtained here indicates the area of the MSI to be rewritten by the vector store instruction. Based on this extracted address, REF
Two search-only FAAs (FAA
2, 3.2, and 6).

Here, assuming that the buffer management of this system adopts the set associative method, in the search, FΔΔ
Examine the necessary entries by changing the column address in sequence. Note that this search is different from a normal FAA search using individual request addresses.A search using individual requests compares all bits of addresses registered in each column, whereas a search using extracted addresses compares all bits of addresses registered in each column. This means that only the bits that have not changed in the request addresses are compared. This enables efficient searching.

The above FA. During A search, if a column that matches the extracted address is detected, FAA23 or 24 is sent to invalidate the data imported into the BS.
(or both), an invalidation processing request for the column is sent. When FAA23.24 receives this request, it invalidates the corresponding power RAM in its own management table, and also disables the FAA and BAA in REF25 and REF26.
30 and 40, a request to invalidate the corresponding power RAM is sent. B.A.
When the FAAs in A30, 40 and REF 25.26 receive this request, they invalidate the appropriate power RAM in their respective management tables. Here, even if invalidation processing is required as a result of searching within REF25 and REF26, directly refer to REF25 and REF26.
, 26, and performs the invalidation process once via FAA 23 or 24. FAA 23.2
FAA23.24 and FAA in REF25.26 due to time difference with FAA registration processing from SP3.4 for 4
This is to prevent discrepancies in the content.

FIG. 8(a) shows the BAA (F
The structure of AA) is shown. In the BS management method in this embodiment, the number of rows is 2 and the number of columns is 16, for example, as a set associative method. The unit of data registration to the BS is a 64-byte block, and the registration address of each entry in the table is 21 bits. Figure 8 et al.] show each bit of the real address and the byte address. It shows the correspondence between intra-block addresses, column addresses, and upper addresses.

FIG. 1 shows the detailed structure related to FAA and REF in SC2.

Registration requests to the FAA sent from SPO and SPI via signal lines 3a and 3b (accompanying the import into BS31.41 of each SP) and invalidation requests (accompanying writing to the MS, BS data in other SPs) Select circuit 2
7 is accepted: N, target FAA (FAA23 or FA
A24> is processed. Here, if the registration request is from SPO and SP1, FAAO (23) and F
Performs registration operation on AAI (24) and sends SPO, S
In response to an invalidation request associated with writing from P1,
Each of FAAI (24) and FAAO (23) checks whether each write address is registered, and if it is registered, invalidates the corresponding en}U. Such processing for the FAA 23.24 is performed when a similar request is sent to the FAA 25A, 25 in the REF 25 via the signal lines 3a, 3b.
B and the FAA in the REF 26 for execution.

On the other hand, in the case of vPO, the store request address sent from VPO and VPI is manually input to address extraction mechanism 250 via signal lines 5a and 5b. Here, the area address where common bits (bits with the same value) are extracted from the multiple addresses is extracted, and the FAA search control mechanism 25
Send to 1.

This FAA search control mechanism 251 searches for the extracted address in each FAA 25A, 25B. If a matching entry is detected in this search process, a request to invalidate the entry is sent to the target FAΔ0 (23) or FAAI (24) via the signal lines 25a, 25b. Upon receiving this request, the selection circuit 27 selects the FA
The relevant en in A} Perform the IJ invalidation process, and then
The same invalidation processing request as the FAA in BAA 30, 40 and REF 25, 26 is sent.

Through the above processing, the invalidation operation of the BSs 31 and 41 in the SPO and SPI in response to the vector store request issued by the VPO is completed, and the consistency of data in the MS and each BS is guaranteed. Note that the above processing is similarly performed using the REF 26 for a vector store request from the VPI.

FIG. 3 shows details of the address extraction mechanism 250. Note that the same applies to the address extraction mechanism 260.

Requests sent from the VPO (5) via the signal lines 5a and 5b are temporarily input to the first-first-first-time stack 7071. Note that in this embodiment, the store requesters 50Δ, 50B, 60A, and 60B are controlled so that the search requests that are manually input to the stacks 70 and 71 at the same time are not mixed with extracted address search requests and individual request search requests. are doing. The requests manually entered into the stack 70, 71 are sequentially taken out in the order in which they were entered, as described above, and are supplied to the subsequent logic. Here the output of the stack is 70a, 7
1a is the FAA search address, and 70b and 7lb are FAA search addresses.
AA search request, 70c, 71c are individual request search requests, 70d, 71d are address extraction start instructions, 70e,
71e is an address extraction end instruction.

Address extraction processing includes individual request search request 7Qc,
When 71C are both "0", stack 70.71
This is accomplished by processing multiple requests simultaneously. The search address 702 is selected by the selection circuit 75 and input to the register 76 .

At the same time, addresses 70a and 71a are
2 is compared bit by bit, and the matching bits are ``1
", the mismatch bit is set as 20" and is set in the valid bit register 77 as extracted valid bit information. Other request signals are output 70 of stack 70.71.
b, 7lb, 70c. 71c, 70d, 71d, 70e
, 71e are logically summed by OR gates 746-749, and set in flip-flops 770-773, respectively. When it is detected that the address extraction process is being performed by the negative extraction of the OR gate 74 becoming "1", the OR gate
742, 743, AND gate 7
4 4745 to instruct each stack 70.71 to update the output pointer.

Next, registers 76, 77 and flip-flop 77
If the request taken out from the stack 70.71 for 0 to 773 includes an instruction to start address extraction processing, this condition is detected by the AND gate 775,
The selection circuit 79 is controlled to select the output of the register 77 to set the extracted valid bit information in the register 781.

Here, for the search address, the value of register 76 is set in register 780 every time. Once the extraction process is started, the search addresses that are sent sequentially are compared to the comparison circuit 78.
Compares bit by bit with the previous address. If the comparison results match, it will be "1", and if they do not match, it will be "0". The output of this comparison circuit 78 and the register 7
The new extracted valid bit information, which is the output of step 7, and the output of the register 781, which is the previous extracted valid bit information, are ANDed bit by bit by an AND gate 784, and the result is set in the register 781 as extracted valid bit ζ information. This process is sequentially repeated until a request with an address extraction end instruction appears. When the address extraction end instruction is detected in the AND game 776, it is sent to the FAA search mechanism 251 via the flip-flop 783 as an extracted address search request 250b. At this time, registers 780 and 781
, respectively, are the extracted addresses 2 5 0 a. It is simultaneously sent out as extracted valid bit information 250v.

On the other hand, when processing individual request search requests, requests from the stacks 70 and 71 are taken out alternately and supplied to subsequent logic. Selection circuit 75 for search addresses 70a and 71a
The selection in is controlled by the output of flip-flop 73, which constitutes a 1-bit counter. If the output of the flip-flop 73 is "0", the address 70a is selected, and if the output is "1", the address 71a is selected. When the search request is selected, if the output of the flip-flop 73 is "0", the inverter circuit 730 → AND gate 7
40→OR gate 742→AND gate 744 to instruct the update of the output pointer of the stack 70. On the other hand, when the output of the flip-flop 73 is "1", the AND gate 741→OR gate 7
43 -> AND gate 745 to instruct the output pointer of the stack 71 to be updated.

Furthermore, during processing of the individual request search request, a 1-bit counter (flip-flop 73) is updated via OR gates 74, 746 and AND gate 739.

Next, when the individual request search request is taken out to the register 76 and flip-flops 770, 771, the outputs of the flip-flops 770, 771 are set to the flip-flop 782 via the AND gate 774, and the individual requests are sent to the FAA search mechanism 251. Request search request signal 250
Send C.

At this time, the search address 250a is also set to registers 76 and 78.
0 to the FAA search engine 251. Note that valid bit information has no meaning here.

Figure 4 shows the FAA search mechanism 251 and FAA25A, 25
Details of B are shown.

First, the operation in the case of extraction address search will be explained. When the extracted address search request 250b is received from the address extraction mechanism 250, the flip-flop 806 indicating that the search process is in progress is set, and the search address 2
50a are set in registers 8oo and goi, and extracted valid bit information is set in register 802, respectively. In addition,
The extracted valid bit information manually entered into the register 802 is partially converted via a conversion circuit 813. This conversion circuit 8
FIG. 5 shows the details of 13. In this circuit,
Valid bits corresponding to 4 bits of column address
For (vQ, Vl, V2, V3 from the top), “00
00'. 1000"1100", 1110
The bit string pattern is converted into a bit string pattern of ".1111", and the target bit is set to "1" only when "■" continues from the upper bit. In other words, only when the AND gate 8132 detects that all 4 bits before conversion are 1'', all bits after conversion are set to 1, and the AND gate 8131 sets the upper 3 bits before conversion to ``1''. 1'', only the upper 3 bits after conversion are set to ``1'', and when the upper 2 bits before conversion are set to ``1'' by AND gate 8130, only the upper 2 bits after conversion are set to ``1'', The upper 1 bit before conversion is “1”
When , only the high-order bit after conversion is set to "1". In other words, this process converts the bits below the bit position of "0" to "0" when there is "0" between "1" in the bit string before conversion.

In addition, the column address manually entered in the register 801 is determined by performing an AND operation on the extracted valid bit information after conversion and the column address in the search address sent via the signal line 250a at the gate 812, and then at the selection circuit 803. Selected and created. Here, the selection circuit 803 controls to select the output signal of the gate 812 only when accepting the extracted address search request 250b.

Once the information necessary for the extracted address search is set, the FAA search is immediately started. Here, if there is no registration/cancellation request from FAA23.24 to FAA25A, 25B, the column address/upper address is the selection circuit 8.
22 to 825 to the FAA 25A, 25B and refer to the management table. Here, the entry of the management table corresponding to the specified column address is read out, and based on the extracted valid bit information of the register 802, the address comparison circuit 25A0.25A1.25B0.25B
1 to compare with the upper address.

FIG. 6 shows details of the address comparison circuits 25AO to 25B1. Register 800 (see Figure 4)
Exclusive OR gate 900 extracts the upper address from the address and the address read from the FAA management table bit by bit.
~902, the output of each gate, extracted valid bit information corresponding to the bit, and AND gates 910~912
The logical AND is performed by the NOR gate 920, and the output of the flip-flop 806 indicating that the search process is in progress is processed by the AND gate 807 and the OR gate}81.
An AND gate 930 performs a logical product with the signal through 0 and uses this as a match signal.

The function of the comparison circuit shown in FIG. 6 is to make a match/mismatch determination only with respect to address bits whose extracted valid bits are "1". When a match is detected in the comparison circuits 25AO to 25B1, the signal lines 25a and 25B1 are
5b to the FAA 23, 24.

When the search for one column address is completed, the column address is incremented by "1" in the adder circuit 804 and set in the column address register 80l again. At this time, the selection circuit 803 controls to select the output of the addition circuit 804.

Further, a set instruction to register 801 generates the output of flip-flop 806 via AND gate 807 and OR gate 8l4. Note that this set instruction is suppressed at the AND gate 807 when there is a registration/cancellation request from the FAA 23.24.

As described above, the column address is sequentially incremented by "1" and the FAA management table is searched accordingly. This increase in column address occurs when all combinations of column addresses of bits whose bit value is "0" in the bit corresponding to the column address of the extracted valid bit information set in the register 802 are calculated. finish. In other words, the adder circuit 8
When a carry occurs within 04, the column address increment is stopped and the FAA search ends. The conditions at this time are
It is generated by the carry signal of each digit of the adder circuit 804 and the information corresponding to the column address in the extracted valid bits, thereby resetting the flip-flop 806 and terminating the FAA search process.

FIG. 7 shows details of the termination condition detection circuit.

Extract valid bit (corresponds to column address)

By ANDing the carry signals of the adder circuit 804 (from the upper order: vO, vl, v2, v3) and the carry signals (from the upper order: cl, c2, c3) using AND gates 8050 to 8052, and further combining them using an OR gate 8053. Detect termination conditions.

The extracted address search process is performed through the series of processes described above.

Next, the operation of the individual request search process will be explained.

In FIG. 4, when the individual request search request 250C is received, the conversion circuit 813 and the OR gate 815 force all extracted valid bits to be in the state of “①” and set this in the register 802. At the same time, the search address is also stored in registers 800 and 801.
Set to .

At this time, the selection circuit 803 is controlled via the OR gate 808 to select the search address 250a.

Further, the individual request search request 250C is sent to the address comparison circuits 25AO to 25B1 via a flip-flop 809 and an OR gate 81O. Here register 8
The address set to 00,804 is selected by the selection circuit 82.
2 to 825 to the FAA management table,
Match/mismatch is determined in the address comparison circuit, and if a match is detected here, an invalidation request is sent to the FAA 23.24. Here, in the individual request search request 250C, there is no need to update the column address, so the process ends here.

In addition, registration to the management table from FAA23.24/
When a cancellation request is sent via signal lines 3b and 4b, the request is set in registers 820 and 821, respectively, and the subsequent selection circuits 822 to 825 are set in registers 820 and 821.
Control is performed to select outputs 0 and 821 to access the FAA management table, and to send the request to AND gate 807 via OR gate 830 to interrupt the extracted address search process.

Through the operations described above, it is possible to perform control to ensure consistency between the BS and the MS in accordance with the execution of vector store instructions from the VPs 5 and 6.

As described above, the FAA search in this embodiment has two modes: extraction address search and individual request search. The individual request search is used, for example, when an extracted address search would take too much time or would likely overly disable the BS. Specific examples in which the advantages of such individual request searches can be utilized will be categorized and explained below.

■The number of seconds required to process with one vector store instruction is small.
, When the overhead is large in the extraction address search, ■ When the increment value of the operand address of one vector store instruction is large and the area of the extraction address becomes large, ■ When the type of target vector store instruction is a list vector store, When the extraction address area becomes large, etc. These conditions apply to store requesters 50A to 51B.
In this step, a determination circuit (not shown) is used to identify the vector length, address increment value, instruction type, etc., and determine which search mode is appropriate. This decision
It is reflected in the individual request search request signal 250C, and the RE
In F25, 26, efficient FA based on the signal
A search is executed.

Furthermore, in this embodiment, it is assumed that the BSs of each SP are in an equal relationship as viewed from the VP, but the SPO and VPO SPI
If and VPI are proceeding with processing in a close relationship, then in the store from VPO, the search for FAAO for SPO is done by individual request search, the search for FAAI for SPI is done by extraction address search, and in the store from VPI, ,SPO
Extract address search for FAAO for SPI
A: Perform the search in 1 using an individual request search,
Control may be performed to improve system performance by suppressing excessive BS invalidation processing.

Furthermore, the address extraction mechanism 250 may be provided on the processor side instead of within the SC2. In this case, it is possible to reduce the amount of interface between the processor and the SC that is involved in the control to guarantee consistency between the BS and the MS, and it is also possible to reduce the amount of hardware involved.

Furthermore, the process of extracting and referring to a search address does not have to be performed in units of bits of the address; it is also possible to control match/mismatch in units of a plurality of bits.

Further, in this embodiment, a processor/server equipped with a vector processing mechanism has been described, but the present invention is also effective in a multiprocessor system not equipped with such a mechanism.

Further, the present invention is effective regardless of the configuration method of the multiprocessor (the connection between the processor and the storage device).

As described above, according to this embodiment, there is no need to provide the number of pages of search FAA for each VP store requester, and half the number of pages of FAA is required.
Since AA can perform efficient search processing, it has a great effect on reducing the amount of hardware.

〔Effect of the invention〕

According to the present invention, the cache (BS) and the shared storage li
The number of registered address management tables in the cache for performing consistency guarantee control with t(MS) can be reduced to less than half that of the conventional technology while maintaining performance, resulting in an efficient system with a small amount of hardware. Memory control becomes possible.

In addition, since the address information for the above-mentioned matching control can be converted into one address that is degenerated (extracted) from a plurality of conventional addresses, the amount of hardware for transmitting the information can be reduced.
It becomes possible to reduce the amount of interfaces according to the degree of degeneracy.

[Brief explanation of the drawing]

FIG. 1 shows a storage control device (SC) according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the detailed structure of the second management table (FAA) and search mechanism (REF) in FIG. The figure is a block diagram showing details of the address extraction mechanism, and Figure 4 shows the FAA search mechanism and second management table (FAA
), FIG. 5 is a block diagram showing the conversion circuit, FIG. 6 is a block diagram showing details of the address comparison circuit, FIG. 7 is a block diagram showing details of the termination condition detection circuit, Figure 8(a) shows the structure of BAA (FAA), and Figure 8(b) shows each bit of the real address, byte address, intra-block address, column address, FIG. 3 is an explanatory diagram showing correspondence with higher-order addresses. 1...Main storage device (MS), 2...Storage control device (SC), 3.4...Scalar processing unit! (SP)3a
... Signal line, 3b... Signal line, 56... Vector processing device, 5a, 5b... Signal line, 23.24...
Second management table (FAA), 25.26... Search mechanism (REF), 25A, 25B... Second management table (FAA) 25A0.25A1... Address comparison circuit, 25a. 25b... Signal line, 27... Selection circuit, 30.31... Buffer storage device (BS), 50
A, 50B...store requester, 60A. 60B・
...Store requester, 70...Stack, 70a.
...Search address, 70b...Output, 70c...Individual request search request, 71...Stack, 71a...
... Address, 72... Comparison circuit, 73... Flip-flop, 74... OR gate, 75... Selection circuit, 76... Register, 77... Valid bit register, 78... Register, 78... Comparison circuit, 7
9... Selection circuit, 250... Address extraction mechanism, 2
50a...Address, 250b...Address search request, 250c...Individual request search request, 250v
...Extraction valid bit information, 251...FAA search mechanism, 251...FAA search control mechanism, 260...
・Address extraction mechanism, 730... Inverter circuit, 7
39 ~ 741 ・ ・ ・ AND gate
, 742, 743... OR gate, 7
44. 745 ・ ・ ・AND gate, 746
・ ・ ・OR gate, 770 ・ ・ ・Flip-flop, 774-776...AND gate, 780
,781...Register, 782,783...Flip-flop, 784...AND gate, 800,80
1... Register, 801... Column address register, 802... Register, 803... Selection circuit, 8
04...Addition circuit, 806...Flip-flop,
807...AND gate, 808...OR gate,
809...Flip flop, 810...O R
Gate, 8 1 2...
Gate, 813...Conversion circuit, 814,
815...OR gate, 820...register, 82
2...Selection circuit, 830...OR gate, 900...
...Exclusive OR gate, 903...AND gate,
910 ・ ・ ・AND gate, 920 ・ ・ ・N
OR gate, 8050 ・ ・ ・AND gate, 80
53 ・ ・ ・OR gate, 8130 ・ ・ ・A
ND gate, 8131...AND gate, 8132...
...AND gate. Agent Patent Attorney Daiwa Tsutsui

Claims (1)

[Claims] 1. Consisting of a main memory and two or more processors that share the main memory, each processor is provided with a buffer memory that holds a copy of a portion of the information in the main memory. In a multiprocessor system, one processor extracts a storage area of the main memory that has been rewritten within a predetermined period, and searches whether the information in the area has been taken into the buffer storage of another processor. , the storage control method is characterized in that, if the information has been imported, the corresponding information in the buffer storage area is invalidated. 2. The storage area of the main memory is extracted by extracting the bit positions and values that did not change in the address of the write request issued by one processor to the main memory within a predetermined period. The storage control system according to claim 1, characterized in that: 3. The storage control according to claim 2, wherein a management table of registration information addresses of a buffer storage device possessed by each processor is sequentially searched for necessary entries based on the address extracted above. method. 4. Claim 2 or 4, characterized in that a search management table for searching for necessary entries based on the address extracted above is provided separately from the management table for the registration information address. 3. The storage control method described in 3. 5. Claim 2, wherein the address is extracted for each block in units of multiple bits and used for the search.
4. The storage control method according to 3 or 4. 6. In a control system comprising a main memory device and a processor equipped with a buffer memory device that holds a copy of a portion of information in the main memory device, when extracting a specific address pattern in the buffer memory device, multiple A storage control method characterized by extracting the positions and values of common bits that do not change from individual addresses. 7. A memory characterized in that when performing a search process between the search data and the table to be searched, the comparison with the search data is performed only with a specific bit position of the entry in the table to be searched, and it is determined whether the two match/mismatch. control method. 8. Add a plurality of vector processing devices each having a store requester to the main memory, and a management table that stores a copy of the main memory and registers the address in the main memory of the stored copy. In a multiprocessor system consisting of a plurality of scalar processing units each equipped with a buffer storage device, by detecting a common bit position and value from the addresses of a plurality of store requests issued from the vector processing unit. , a means for extracting an address indicating a stored area, and a management table of the buffer storage device in order to determine whether information of the extracted address area has been taken into the buffer storage device in each scalar processing device. A storage control method having means for searching and means for invalidating the information if it has been captured. 9. First search for extracting addresses indicating the main storage area targeted by multiple store requests from the vector processing device to the main storage device and searching the management table corresponding to the buffer storage device in each scalar processing device means and second search means for searching the management table using addresses of individual store requests from the vector processing device to the main memory, and a second search device for searching the management table using addresses of individual store requests issued from the vector processing device. 9. The storage control system according to claim 8, further comprising a selection means for employing the first or second search means depending on various conditions.