JPH10247182A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor system which can improve the efficiency by reducing the load on a system bus and reducing the limit of the number of processors which can be mounted. SOLUTION: Processor groups 1 and 2 consists of processors 11, 12, 21 and 22, input/output processors 13 and 23 and common buffer parts 14 and 24 and the processors 11, 12, 21 and 22 and the input/output processors 13 and 23 are connected to a system bus 100 through the common buffer parts 14 and 24. The common buffer parts 14 and 24 can be accessed by the processors 11, 12, 21 and 22 and the input/output processors 13 and 23 freely in common and are a high-speed buffer mechanism for holding data stored in a storage device 3 and data for executing reading out of and writing in an external device. A request to access the data held by the common buffer parts 13 and 24 is controlled by a store-in system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiprocessor system, and more particularly to a method for reducing a system bus load in a highly parallel processor.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, as shown in FIG.
2, 51, 52 and the input / output processor 6 are connected to the system bus 1
00 to access the storage device 3.

Each of the processors 41, 42, 51, 52 is disposed in each of the processor groups 4, 5, and the shared buffers 43, 4 disposed in each of the processor groups 4, 5, respectively.
It is connected to the system bus 100 via 53.

In the system having the shared buffers 43 and 53 as described above, the purpose of arranging the shared buffers 43 and 53 is to improve the access performance of the storage device 3 and is positioned as a cache of the storage device 3. Therefore, the configuration is such that the shared buffers 43 and 53 are interposed between the system bus 100 and the storage device 3.

[0005]

In the conventional multiprocessor system described above, a system bus is always used every time a memory access is performed from each processor to a storage device. The bus load suddenly increases.

In the data fetch processing from each processor, if there is no data to be sought on the storage device,
The secondary storage device such as a magnetic disk device mounted thereunder is accessed via the input / output processing device. In that case, data read from the secondary storage device by the input / output processing device is temporarily held in the storage device via the system bus, and is transferred from the storage device to the requesting processor via the system bus by the memory access processing. .

Therefore, the load on the system bus becomes very high, and the number of processors that can be efficiently mounted is up to 10 due to the performance limitation due to the load on the system bus.
It will be limited to a platform.

The shared buffer is used for complementing the data reading and writing processing in the storage device because the processing is slower than the processing capability of the processor.
Since reduction of the load on the system bus is not considered, even if a shared buffer is provided in the system, the load on the system bus cannot be reduced by the shared buffer.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to reduce the load on the system bus, and to improve the efficiency by reducing the limit on the number of processors that can be mounted. It is to provide a system.

[0010]

According to the present invention, there is provided a multiprocessor system comprising: a plurality of processors; data provided between each of the plurality of processors and a system bus; and input / output to / from each of the plurality of processors. A shared buffer that holds an input / output processing device that is connected to the system bus via the shared buffer and controls input / output processing between an external device and each of the plurality of processors. Have.

In another multiprocessor system according to the present invention, in addition to the above-described configuration, the multiprocessor system includes a plurality of processor groups each including a pre-assigned processor among the plurality of processors, and the shared buffer stores the plurality of processors. They are located in each group.

That is, in the multiprocessor system of the present invention, the store-in type shared buffer is located between the processor and the system bus. This makes it possible to reduce the frequency of access to storage devices accessed via the system bus, so that even if a multi-processor configuration is used, the number of processors that can be mounted can be reduced without imposing an excessive load on the system bus. Can be increased.

Further, by configuring the input / output processing devices arranged in each processor group to be connected to a system bus via a shared buffer, the input / output processing device can be configured to store data once the data is written to the shared buffer. Since the processing can be completed, it is not necessary to send all access requests to the storage device via the system bus, so that the load on the system bus can be reduced.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, processor groups 1 and 2 are processors 11, 12, 21, and 22, respectively.
, I / O processing devices 13 and 23, and shared buffer unit 1
4, 24, and processors 11, 12, 2
1 and 22 and the input / output processing devices 13 and 23 are connected to the system bus 100 via the shared buffer units 14 and 24. The storage device 3 is connected to the system bus 100 in addition to the processor groups 1 and 2.

The processors 11, 12, 21, and 22 are processing mechanisms for executing tasks which are units of processing. The input / output processing devices 13 and 23 are devices for controlling an access process to an external device (not shown) such as a magnetic disk device (hereinafter referred to as an I / O (input / output) process).

The storage device 3 includes processors 11, 12, 2
This is a storage mechanism for holding data used by the storage devices 1 and 22. The system bus 100 is connected to the shared buffer unit 14,
24 is a bus connecting the storage device 3 and the storage device 3.

The shared buffer units 14 and 24 include the processor 1
1, 12, 21, 22 and the input / output processing units 13, 23
Are a common high-speed buffer mechanism for holding data stored in the storage device 3 or data read / written to / from an external device. still,
An access request to the data held in the shared buffer units 14 and 24 is controlled by a store-in method. Also,
The store-in method is a control method similar to the write-back method described in JP-A-63-244150, and the control method is described in detail in the publication.

In FIG. 1, processor groups 1 and 2
Although the number of processors in 2 is the same, the number does not need to be the same. For example, a processor group of only one processor, a processor group of three processors, or a processor group of five processors I don't care. In any of the processor groups, it is sufficient that the processor group includes a processor and a shared buffer unit that can be shared by the processors.

The number of the input / output processing devices 13 and 23 arranged in the processor groups 1 and 2 does not need to be one in each processor group. Need not be the same. Further, the input / output processing device needs to be connected to the system bus via the shared buffer unit, and can be connected to the shared buffer unit even when the processor is not connected to the shared buffer unit.

FIG. 2 is a block diagram showing the configuration of the shared buffer unit 14 of FIG. In the figure, shared buffer unit 1
Reference numeral 4 includes a shared buffer 14a and an input / output control unit 14b.

The input / output control unit 14b includes processors 11, 1
2, the input / output processor 13 and the system bus 100, respectively.
Address match detection according to a read / write command input from the system bus 100 and a match control between other shared buffer units 24 [for example, using a dedicated path (not shown) or the system bus 100]. Control, etc.).

In this case, the input / output control unit 14b controls an access request to the data held in the shared buffer 14a by a store-in method. Although not shown,
The shared buffer unit 24 has the same configuration as the shared buffer unit 14, and performs the same control as the shared buffer unit 14.

FIG. 3 is a diagram showing the flow of data in the memory access process when a data request is made from the processor 11 of FIG. 1 to the storage device 3, and FIG. 4 is a diagram showing the flow of data from the processor 11 of FIG. FIG. 7 is a diagram showing a data flow when data is written to a processor group, and a data flow when the processors 21 and 22 of another processor group 2 need the data.

FIG. 5 shows an input / output processor 13 when an I / O request is made from the processor 11 to the input / output processor 13.
FIG. 4 is a diagram showing a flow of data from a. These FIGS. 1 to 5
The operation of the embodiment of the present invention will be described with reference to FIG.

When a memory access occurs due to a request such as an instruction fetch or an operand fetch from the processor 11, first, the presence or absence of the corresponding data is checked in the shared buffer unit 14. Access to the storage device 3 occurs as in the path in FIG. The data read from the storage device 3 returns in the order shown in FIG. 3 in the reverse order, and is stored in the shared buffer unit 14 and transferred to the requesting processor 11, thereby completing the memory access process.

When the data read from the storage device 3 is requested by the processors 11 and 12 in the memory access processing, when the memory access is issued, the data is already held in the shared buffer unit 14. By reading data from the shared buffer unit 14, the memory access processing is completed (pass in FIG. 3). In this case, no memory access to the storage device 3 via the system bus 100 occurs.

Next, when data is written from the processor 11, if a data block to be written exists in the shared buffer section 14 as shown in the path of FIG. Is written, and the data writing process ends.

However, if the data block to be written does not exist in the shared buffer unit 14, the data block is once read from the storage device 3 and held in the shared buffer unit 14, and then the write data from the processor 1 is stored in the shared buffer unit 14. Write and update processing to the write target area. These series of processes can be fully understood from the processing procedure usually taken when the shared buffer units 14 and 24 adopt the store-in cache control as described above.

When data is updated in the shared buffer unit 14 by the above-described data writing process, if the shared buffer unit 24 also holds a data block to be written, data matching control is performed. As the coincidence control, a dedicated path or the like provided for writing monitoring between the shared buffer units 14 and 24 or the system bus 100 is used.
And the like by monitoring the address of the write data block.

Further, when the processor 21 requests data of a data block updated by data writing by the processor 11, the updated data block stored in the shared buffer unit 14 is stored as shown in the path of FIG. The data is transferred to the device 3 and the shared buffer unit 24 for writing. The processor 21 accesses the data block written in the shared buffer unit 24 to read the data, and ends the data request processing.

Next, the input / output processing device 13 is
When I / O processing is performed by a data request from
The data from the input / output processing device 13 is temporarily stored in the shared buffer unit 14, as shown by the path in FIG. Thereafter, data in the shared buffer unit 14 is read out in the form of memory access in the same manner as in the above-described path of FIG.
The processing of the data request ends.

Therefore, in the I / O processing for the input / output processing device conventionally performed via the system bus 100, the I / O processing is performed without using the system bus 100.
The I / O processing can be completed.

The input / output processing device 13 is a processor 1
When the processor 21 requests the data read by the I / O processing performed in response to the data request from the processor 1 and held in the shared buffer unit 14, the data is held in the shared buffer unit 14 as shown by the path in FIG. Is stored in the storage device 3 and the shared buffer unit 2 via the system bus 100.
Written in 4.

When the writing of data to the shared buffer unit 24 is completed, the processor 21 reads the data from the shared buffer unit 24 in the form of memory access in the same manner as in the path of FIG. 2, and completes the processing.

FIGS. 6 and 7 are flowcharts showing the operation at the time of memory access according to an embodiment of the present invention, and FIG. 8 is a flowchart showing the operation at the time of an I / O request according to an embodiment of the present invention. The operation at the time of memory access and the operation at the time of an I / O request according to an embodiment of the present invention will be described with reference to FIGS.

When a memory access occurs due to a request such as an instruction fetch or an operand fetch from the processor 11, first, the presence or absence of the corresponding data is checked in the shared buffer unit 14 (steps S1 and S2 in FIG. 6). For example, the corresponding data is sent from the shared buffer unit 14 to the requesting processor 11 (step S in FIG. 6).
3). In this case, the input / output control unit 1 of the shared buffer unit 14
4b suppresses a memory access request from the processor 11 to the storage device 3.

On the other hand, if there is no corresponding data, an access request from the processor 11 to the storage device 3 is sent to the input / output control unit 14b of the shared buffer unit 14 and the system bus 10
0 to the storage device 3 (see the path in FIG. 3).

In this case, if the latest data is stored in the storage device 3 (step S4 in FIG. 6), the data read from the storage device 3 returns in the reverse order of the path in FIG. 3, and the data is stored in the shared buffer 14a. It is held and transferred to the requesting processor 11 (step S5 in FIG. 6), and the memory access processing is completed.

On the other hand, if there is no latest data in the storage device 3 (step S4 in FIG. 6), a shared buffer holding the latest data (for example, the shared buffer unit 24 of another group).
The data is read from the storage device 3 and transferred to the storage device 3 and the shared buffer unit 14 of the own group, and is also transferred to the processor 11 to complete the memory access processing (step S6 in FIG. 6).

When data is written from the processor 11 and there is no data block to be written in the shared buffer unit 14 (step S1 in FIG. 6, step S7 in FIG. 7), the data block is stored in the storage device 3. Once and read out from the shared buffer unit 14 (step S8 in FIG. 7), the processor 11
Is written (step S9 in FIG. 7).

If a data block to be written exists in the shared buffer section 14 (step S7 in FIG. 7), the data from the processor 11 is written into the write target area (step S9 in FIG. 7).

After the data writing process is completed,
The input / output control unit 14b of the shared buffer unit 14 transfers the write data address to the shared buffer unit 24 and the storage device 3 of another group (Step S10 in FIG. 7). Thereafter, the input / output control unit 14b invalidates the data block in the shared buffer unit 24 and the storage device 3 (for example, clears the V bit) (Step S11 in FIG. 7).

When an I / O request is generated, the processor 11 sends a data request to the input / output processing device targeted for the I / O request (step S21 in FIG. 8).

When the input / output processing device performs an I / O process in response to a data request from the processor 11, data from the input / output processing device is transferred to the shared buffer unit 1 of the group.
4 and 24 (step S22 in FIG. 8). Since the request source processor 11 belongs to its own group (step S23 in FIG. 8), the shared buffer unit 14 reads out the data held in the shared buffer 14a, and
(Step S24 in FIG. 8).

On the other hand, since the requesting processor 11 does not belong to its own group (step S23 in FIG. 8), the shared buffer unit 24 of the other group reads out the held data and reads the storage device 3 and the shared buffer unit 14 of the other group. And the data is transferred to the requesting processor 11, thereby completing the data request process (step S25 in FIG. 8).

As described above, the processors 11, 12, 2
1 and 22, and the input / output processing units 13 and 23 are connected to the system bus 100 via the shared buffer units 14 and 24, so that the processors 11, 12, 21 and 21, Conventionally, the system bus 100 is used twice before the data is transferred to the shared buffer unit 22, but the frequency is changed to the processors 11, 12, 2 connected to the same shared buffer units 14, 24.
If it is an I / O processing request from the I / O processing unit 1 or 22, it can be suppressed to zero.

Further, a plurality of processors 11, 12, 2
Since the shared buffer system in which the buffers are shared by the processors 1 and 22 is used, the memory access can be reduced as compared with a system having a second cache for each processor, and the load on the system bus 100 is reduced. Can be achieved.

Therefore, since the usage rate of the system bus 100 can be reduced, the load on the system bus 100 can be reduced, and the performance of the system bus 100 can be improved as compared with other equivalent systems. Can be connected, so that a highly parallel system with a large-scale configuration can be realized.

[0049]

As described above, according to the present invention, a plurality of processors, and a shared processor disposed between each of the plurality of processors and a system bus and holding data input / output to / from each of the plurality of processors. In a multiprocessor system including a buffer, a load on the system bus is provided by providing an input / output processing device connected to the system bus via a shared buffer and controlling input / output processing between an external device and each of the plurality of processors. And the efficiency can be improved by reducing the limit on the number of processors that can be mounted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a shared buffer unit of FIG. 1;

FIG. 3 is a diagram showing a data flow by a memory access process when a data request is made from the processor of FIG. 1 to a storage device.

FIG. 4 is a diagram showing a data flow when data is written from the processor of FIG. 1 to the storage device and a data flow when the data is needed by a processor of another processor group.

FIG. 5 shows an I / O from the processor of FIG. 1 to an input / output processing device;
FIG. 9 is a diagram showing a flow of data from the input / output processing device when an O request is made.

FIG. 6 is a flowchart showing an operation at the time of memory access according to an embodiment of the present invention.

FIG. 7 is a flowchart showing an operation at the time of memory access according to an embodiment of the present invention.

FIG. 8 is a flowchart showing an operation at the time of an I / O request according to one embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 processor group 3 storage device 11, 12, 21, 22 processor 13, 23 input / output processing device 14, 24 shared buffer unit 14a shared buffer 14b input / output control unit 100 system bus

Claims (4)

[Claims] 1. A multiprocessor system comprising: a plurality of processors; and a shared buffer disposed between each of the plurality of processors and a system bus and holding data input to and output from each of the plurality of processors. hand,
A multiprocessor system, comprising: an input / output processing device connected to the system bus via the shared buffer and controlling input / output processing between an external device and each of the plurality of processors. 2. The apparatus according to claim 1, further comprising: a plurality of processor groups each including a pre-assigned processor among the plurality of processors, wherein the shared buffer is arranged in each of the plurality of processor groups. Multiprocessor system. 3. The multiprocessor system according to claim 2, wherein said input / output processing device is connectable to said shared buffers provided for each of said plurality of processor groups. 4. The multiprocessor system according to claim 1, wherein an access request to data held in said shared buffer is controlled by a store-in method.