JPH01223545A - Buffer memory - Google Patents

Abstract

PURPOSE:To increase the probability that request data exist in a buffer memory and to improve the use efficiency of a bus by providing an adder means to add the block size of a data memory, a comparing means, a buffer memory control means, etc. CONSTITUTION:After the request address from an I/O is stored from an input output bus 6 through an input output bus interface 21 to an input output address register 19, it is compared with the address information read from a directory memory 12 by a comparator 14. As the result, at the time of non-consistency, a buffer memory control part 11 adds a block size (k) to an address in the register 19 with an adder 16 and it is decided with the address after adding whether or not the data exist in a buffer memory 11. As the result, when the data are absent, the control part 11 outputs the address after adding to the bus 6, requests the data and thus, the data read from a main memory device are, written and updated to the memory 12 and a data storing memory 13. Consequently, the probability that the request data exist in the device 1 is increased and the use efficiency of the bus 6 can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer storage device, and particularly to a buffer storage device provided between an input/output control section and a main memory.

[Conventional technology]

Conventionally, FIFO has been used as a buffer device provided between an input/output control device and main memory. The idea was to incorporate this into the input/output control unit to absorb the difference in speed between the connected device and the main memory.

Also, the buffer storage device has a data width (block size) that is wider than the data width requested by the request source.

It is read from main memory and stored in buffer memory.

[Problem to be solved by the invention]

However, recently, there has been an increase in the number of devices that connect the main memory and the input/output control section through a path. In the case of a format in which a high-speed main memory path and an input/output bus are connected by a bus coupling device, incorporating FIFOs into the bus coupling device requires work to determine the number of FIFOs and allocate them to data transfer devices. or,
Cache memory, which has traditionally been used in central processing units, checks whether or not there is data in a block for continuous access by one peripheral device, and if it does not, fetches data equivalent to the block size. Because it works, it only works as a FIFO for the block size.

The effect was low.

In view of the above drawbacks, a technical object of the present invention is to provide a buffer storage device that increases the probability that requested data exists in the buffer storage and improves the bus utilization rate.

[Means for Solving the Problems] That is, according to the present invention, in addition to the ordinary cache memory, there is also a means for adding the block size of the data memory to the request address, and the result is stored in the directory memory. A buffer memory that accesses the main memory using the addition result and rewrites the contents of the data memory and the directory memory with the data read from the main memory and the addition result when there is a mismatch. A buffer device characterized in that it has a control means is obtained.

〔Example〕

Next, a buffer storage device according to a ninth embodiment of the present invention will be described with reference to two drawings.

FIG. 2 is a schematic diagram of an information processing system to which the present invention is applied. This system consists of a buffer storage device 1. Central processing unit 2. It is composed of a main storage device 3 and an input/output control device 4, each having a memory path 5. and are interconnected by an input/output bus 6.

When the input/output control device 4 reads memory data, it issues a data request to the input/output bus 6. Upon receiving this data request, the buffer storage device 1 checks whether data exists within itself, and if it exists, the data in the buffer storage device 1 is input/output via the input/output bus 6. Transfer to the control device 4. However, if there is no data in the buffer storage device l, a read request is issued to the memory path 5 along with an address. In response to this read request,
The data specified by the address is read from the main storage device 3 and transferred to the input/output control device 4 via the input/output bus 6. At the same time, it is also stored inside the buffer storage device.

Following the above operations, the buffer storage device 1 of this embodiment adds the block size to the requested address, checks again whether or not data exists in its own device, and if so, ends the operation. If it does not exist, a read request is issued to the memory path 5 using the address after the addition. When data is read from the main memory device 3 in response to this read request, it is stored in the memory within the buffer device 1. In this way, preparation for the next access is made within the buffer device.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure.

Buffer storage device 1 is connected between input/output bus 6 and memory path 5 . The buffer storage device 1 includes a buffer storage control section 11. Directory memo! j12j data storage memory 13. Comparator 14. Address selection circuit 15. Multiplexer 17. and memory interface 1
8. Address register 19. data register 20,
It is composed of an I10 bus interface 21.

In the embodiment configured in this way, the requested address from the I/Q device is stored in the input/output address register 19 via the input/output bus interface 21 from the input/output bus. It is compared with the address information read from directory memory 12 to determine whether the data at the requested address is in buffer storage l. If they match, a match signal is supplied from the comparator 14 to the buffer storage controller 11. As a result, the buffer storage control unit 11 reads data from the data storage memory 13 and simultaneously controls the multiplexer 17 to read the data to the data register 20. The read data is output to the input/output path via the input/output bus interface and sent to the 1st offshore control unit.

On the other hand, when the two outputs of the comparator 14 do not match, upon receiving the mismatch signal from the comparator 14, the buffer storage control outputs a data request signal, and the path interface outputs the read address to the path. Then, the data is read from the main storage device 3. The read data is sent to the pass through multiplexer 15. At the same time, upon receiving an instruction from the buffer storage control section 11, the current read address information is written into the directory memory 12, and the data is written into the data storage memory 13, respectively. After that, the buffer storage control unit 11 switches the multiplexer 15 to add the block size k to the address of the address register 19 using the adder 16, and again, the data is stored in the buffer storage device at the address after the addition. Determine whether it is within the range. If the outputs of the comparator 14 match, no further operation is performed. When the output of the comparator 14 indicates a mismatch, the buffer storage control unit 11 outputs a data request signal, and the path interface 21 outputs the address after addition to the path.

Main memory device 3 reads data. According to instructions from the buffer storage control unit 11, read address information of the read data is written in the directory memory 12, and data is written in the data storage memory 13, respectively.
Updated.

〔Effect of the invention〕

As explained above, the present invention provides a buffer storage device with:
Adding an adder, further controlling to add the block size to the requested address, and determining whether data for the address after 270 calculations exists in the buffer storage device,
If there is no data, access the main memory using the address after addition.

By updating the contents of directory memory and data memory in buffer storage, like an input/output control house,
For devices that transfer data to contiguous memory areas,
This has the effect of increasing the probability that the requested data exists in the buffer memory. In addition, since the probability that the information exists in the buffer memory increases, the time that one control unit occupies the input/output path is shortened, which has the effect of increasing the path utilization rate.

[Brief explanation of the drawing]

FIG. 1 is a detailed block diagram of the present invention, and FIG. 2 is a configuration diagram of an information processing system including the apparatus of the present invention. l...Buffer storage device, 2...Central processing unit, 3
...Main storage device, 4...I/O control device, 5...
Memory path, 6... Input/output path, 11... Buffer storage control unit, 12... Directory memory, 13...
・Data storage memo! 7115...Multiplexer, 1
6...Adder. 18...Memory path interface, 21...Input/output bus interface. Figure 1

Claims (1)

[Claims] 1. a data memory that stores a copy of the data in the main memory, and an address in the main memory that corresponds to the copy of the data;
Or a directory memory that stores part of the address,
The requested address from the data request source is compared with the address stored in the directory, and when the comparison results match, a copy of the data is supplied from the data memory to the request source, and if the comparison result does not match. At the time of , a buffer memory supplies read data from the main memory according to the read address to the request source and rewrites the contents of the data memory and the contents of the directory memory with the read data and the read address, respectively. In the apparatus, an addition means for adding a block size of the data memory to the requested address, a comparison means for comparing the result of addition by the addition means with an address stored in the directory memory, and When there is a mismatch, the main memory is accessed using the addition result, and the buffer memory rewrites the contents of the data memory and the directory memory with the address after the addition with the read data from the main memory. A buffer storage device comprising a control means.