JPH02112039A - Buffer storage device - Google Patents

Abstract

PURPOSE:To improve the efficiency of a buffer storage device by adding a block-end address detector to the buffer storage device and controlling the storage device so as to turn off the effective bit of the buffer memory when a requesting address is a block-end address. CONSTITUTION:A requesting address from an I/O device is stored in an input- output address register 18 and compared with address information read out from a directory memory 12 for discriminating whether or not the data of the request address exist in a buffer storage device 1. When the data of the address exist in its own device, the lower address of the requested address for making next operations is further checked. When the requested address indicates the last of a block, the data are transferred and, at the same time, an invalidate bit is set to the block just read out. Thus the transferred block is utilized when the content of the buffer storage device is exchanged next. Therefore, the expelling frequency of data for low-speed operations from the buffer storage device is reduced and the buffer storage device operates effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer storage device, and particularly to a buffer storage device between an input/output control section and a main storage section.

[Prior art and problems to be solved by the invention] Conventionally,
FIFO was used as a buffer storage device between the input/output control section and the main storage section. The idea was to incorporate this into the input/output control section to absorb the difference in speed between the connecting device and the main memory section. Further, the buffer storage device reads data from the main storage section with a data width (block size) wider than the data width requested by the data requesting device, and stores the data in the buffer storage device. With this method, the memory of the input/output device,
FI for block size for continuous access to rear
Although it operates as an FO, if a low-speed device and a high-speed device operate at the same time, the data for the high-speed device will be read out and stored in the cache for the low-speed device before all the data stored in the cache is transferred. Replaced by For this reason, a problem occurred in that the prepared buffer did not work sufficiently.

Furthermore, in the case of a FIFO format buffer configuration, it was necessary to manage the number of FIFOs and allocate them to data transfer devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer storage device that works effectively in a system in which a high-speed human output control section and a low-speed human output control section coexist.

[Means for Solving the Problems] A buffer storage device according to the present invention transfers data to a cache memory in response to a request address when the data is the last data in a block of data memory of the buffer storage device, and at the same time transfers data to a cache memory in response to a request address. It provides means for setting an invalid bit in the directory pointing to the block in memory. As a result, the frequency with which low-speed data is evicted from the buffer storage device is reduced, and the buffer storage device operates effectively.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a schematic configuration diagram of an information processing system to which the present invention is applied. This system includes a buffer storage device 1,
It is composed of a central processing unit 2, a main storage device 3, and an input/output control device 4, each of which is interconnected by a memory data and input/output bus 6.

When the human output control device 4 reads memory data, it issues a data request to the input/output bus 6. The buffer storage device 1 that has received this data request checks whether or not the data exists within itself, and if so, transfers the data in the buffer storage device 1 to the input/output control device via the input/output bus 6. Transfer to 4. However, if there is no data in the buffer storage device 1, a read request is issued to the memory bus 5 along with an address. In response to this read request, the data specified by the above address is read from the main memory 3 to the buffer memory 1, and further to the human output control device 4.
will be forwarded to. At this time, the data inside the buffer storage device 1 is also updated.

The buffer storage device of the present invention further examines the lower part of the address where the next operation is to be performed when there is data at the address in the own device, and transfers the data when the end of the block is reached, while at the same time reading out the current data. Sets the invalid bit of the block.

In this way, the block that has been transferred can be used the next time the contents of the buffer memory are replaced.

FIG. 1 is a block diagram showing the configuration of a buffer storage device according to an embodiment of the present invention.

In FIG. 11, the buffer storage 1 is connected to the human output bus 6.
and the memory bus 5.

The buffer storage device 1 includes a buffer storage control section 11, a directory memory 12, a data storage memory 14, and a comparator 1.
5, multiplexer 17, memory bus interface 2
0, an address register 18, a data register 19, and an I10 bus interface 21.

In embodiments so constructed, the requested address from the I10 device is stored in the human output address register 18. In order to determine whether the data at the requested address is in the buffer storage device 1, it is compared with the address information read from the directory memory 12. When the two match, a match signal 151 is supplied from the comparator 15 to the buffer storage control section 11. by this,
The buffer storage control unit 11 reads data from the data storage memory 14 and simultaneously controls the multiplexer 17 to read the data to the data register 19. The read data is output to the input/output bus 6 via the input/output bus interface 21 and sent to the I10 control section. or,
The read address is checked by a comparator 15 to see if it is a block end address, and if it is a block end address, the buffer storage control section 11 turns off the valid bit corresponding to the corresponding block address in the valid bit memory 13 in response to the detection signal 161.

When the two outputs of the comparator 15 do not match, or even when they match but the valid bit is off, the buffer storage control section 11 outputs a data request signal, and the memory bus interface 20 outputs the read address to the bus controller. , reads data from the main storage device 3. The read data is sent to the human output bus 6 through the multiplexer 17. At the same time, in response to an instruction from the buffer storage control unit 11, the current read address information is written into the directory memory 12, the data is written into the data storage memory 14, and the corresponding block address in the valid bit memory 13 is written. Turn on the enable bit.

[Effects of the Invention] As described above, the present invention adds a block end address detector to the buffer storage device, and controls the valid bit of the buffer memory to be turned off when the requested address is the block end address. This allows data transfer to be performed from one continuous memory area to another, like an input/output control device.
For devices that only perform rotations, it is possible to control unnecessary data so that it does not stay in the buffer memory, and even when a high-speed input/output control section and a low-speed human output control section operate at the same time, data from the low-speed control section This has the effect of reducing the probability that the buffer storage device will be evicted from the buffer storage device, thereby increasing the efficiency of the buffer storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a buffer storage device according to an embodiment of the invention, and FIG. 2 is a block diagram showing the configuration of an information processing system including the buffer storage device of the invention. 1... Buffer storage device, 2... Central processing unit, 3
...Main storage device, 4...I/O control device, 5...
Memory bus, 6... Input/output bus, 11... Buffer storage control unit, 12... Directory memory, 13...
・Valid bit memory, 14...Data storage memory, 1
5... Comparator, 16... Comparator, 18... Address register, 19... Data memory, 20... Memory bus interface, 21... I10 bus interface. Figure 1

Claims (1)

[Claims] 1. A data memory for storing a copy of data in the main memory;
A directory memory that stores an address or a part of the address of the main memory corresponding to a copy of the data, and a read address supplied when reading from the data requesting device and an address stored in the directory are compared. and a comparison means for supplying a copy of the data from the data memory to the data requesting device when the comparison results match, and when the comparison results do not match, read data from the main storage section according to the read address. A buffer storage device that supplies data to a data requesting device and rewrites the contents of the data memory and the directory memory with read data and a read address, respectively, wherein the data to be transferred according to the request address is stored in the data memory of the buffer storage device. A buffer storage device characterized in that an invalid bit in a directory pointing to the block in a directory memory is set at the same time as data is transferred at the time of the last data in the block.